RTL Design Engineer

Acceler8 Talent; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is seeking a hands-on Staff, Senior Staff, or Principal RTL Design Engineer for a seed AI hardware startup building a dedicated LLM inference ASIC. You will own a substantial RTL scope and translate microarchitecture into synthesizable RTL, collaborating with verification and physical-design teams near Palo Alto.

Strong Verilog/SystemVerilog skills are essential; AI accelerator or inference ASIC experience is preferred, with deep digital-silicon know-how and a proven track record

Qualifications

• Strong Verilog or SystemVerilog skills are essential.
• AI accelerator or inference ASIC experience is preferred, with strong adjacent digital-silicon experience also relevant.
• Hands-on experience delivering substantial ASIC or SoC RTL.

Responsibilities

• Translate microarchitecture into synthesizable RTL, with ownership of a substantial design scope.
• Design and debug datapaths, control logic and block interfaces.
• Collaborate with verification and physical-design engineers to resolve issues and tapeout readiness.

Skills

RTL design

Verilog/SystemVerilog

ASIC/SoC RTL delivery

Digital silicon design

Tools

EDA tools

Job description

Hiring: Staff / Principal RTL Design Engineer | LLM Inference ASICs

I’m partnering with a seed-funded AI hardware startup building a dedicated LLM inference chip and the software stack around it.

The founding team combines Stanford AI research with silicon experience from NVIDIA, Groq and Google’s TPU team. With tens of millions raised, they’re expanding their early hardware team.

What you’ll own

• Translate microarchitecture into synthesizable RTL, with direct ownership of a substantial design scope.
• Design and debug datapaths, control logic and block interfaces.
• Work closely with verification and physical-design engineers to resolve correctness issues and implementation constraints through tapeout readiness.

Who we’re looking for

A hands-on Staff, Senior Staff or Principal-level engineer who has personally delivered substantial ASIC or SoC RTL and can explain the difficult logic problems they solved.

Strong Verilog or SystemVerilog skills are essential. AI accelerator or inference ASIC experience is preferred, with strong adjacent digital-silicon experience also relevant.

South Bay, around Palo Alto / Menlo Park | Full-time in office

An opportunity to shape a new inference platform while staying close to detailed engineering.