RTL Design Engineer

Etched; San Jose (CA); On-site; USD 150,000 - 275,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving medical benefits

Housing subsidy of $2000 per month

Relocation support

Daily lunch + dinner

Job summary

A technology firm based in San Jose is seeking an experienced RTL Engineer who will focus on design verification of cutting-edge AI chips. Candidates should have at least 5 years of experience in RTL development and be proficient in high-speed digital logic. This role requires a quick learner willing to work in a dynamic environment, contributing significantly to the firm’s success. Competitive compensation is offered, with strong benefits tied to wellness and relocation support.

Qualifications

• At least 5 years of work experience in RTL development.
• Experience with high-speed digital logic.
• Proficiency in standard RTL design and synthesis tools.
• Familiarity with verification work and writing test benches.
• Willing to learn quickly about transformers and modern AI.

Responsibilities

• Develop and implement design verification strategies for ASIC designs.
• Ensure the AI chips operate correctly and efficiently.
• Provide feedback to ensure blocks meet timing and area constraints.

Skills

RTL development

High-speed digital logic

RTL design and synthesis tools

Verification work

Quick learner

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs. In this role, you will work closely with state‑of‑the‑art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast‑paced environment with a high degree of autonomy, and be responsible for a key part of Etched’s success.

Representative Projects

• Implement a block to efficiently compute floating point math operators
• Provide feedback to the uArch team to make sure blocks meet timing and area constraints

You may be a good fit if you

• At least 5 years of work experience in RTL development.
• Experience with high‑speed digital logic.
• Proficiency in standard RTL design and synthesis tools.
• Familiarity with verification work and writing test benches.
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence.
• Willing to start quickly.

Strong Candidates May Also Have Experience With (Nice‑to‑have Qualifications)

• Experience with PCIe, Ethernet, or HBM technologies.
• Familiarity with transformer models and machine learning.
• Familiarity with numerical representations and functions.
• Ability to program with Python or another scripting language.

We encourage you to apply even if you do not believe you meet every single qualification.

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office

How We’re Different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.

We are a fully in‑person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Compensation Range: $150K - $275K