Founding RTL Design Engineer

80Twenty; San Francisco (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Competitive compensation

Startup equity upside

High visibility

Job summary

A startup in cutting-edge AI hardware in San Francisco is seeking a Design Engineer to define and build RL environments and contribute to hardware engineering automation. The candidate should have 4–10+ years of RTL experience and strong debugging and scripting skills. This is a full-time position offering competitive compensation in a high-impact environment. Join the founding engineering team to influence product development and company success.

Qualifications

• 4–10+ years of RTL design or verification experience using System Verilog.
• Strong debugging and automation skills are required.
• Experience in fast-moving startup environments.

Responsibilities

• Define and build the RL environment and product catalog.
• Manage a team to design and verify modules and SoCs.
• Collaborate with AI researchers to automate hardware engineering tasks.

Skills

RTL design or verification experience

Strong debugging skills

Scripting (Python/TCL)

Collaboration across teams

Automation skills

Tools

System Verilog

Industry-standard flows

Job description

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This range is provided by 80Twenty. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$180,000.00/yr - $250,000.00/yr

Direct message the job poster from 80Twenty

80Twenty is a boutique technical recruitment agency that connects high-growth companies with exceptional candidates.

This is onsite in SF.

Join our cutting edge start up client who is distrusting the hardware engineering design workflow by creating AI training environments that will scale hardware engineering knowledge.

They say chip design never got its GPT moment as there is no training data: 99% of RTL data is closed-source. Software engineers can use Cursor to 10x their productivity, but hardware engineers can’t do the same. OpenAI and Anthropic want to automate chip design and verification, but they can’t with no data. This is the bottleneck preventing AI from transforming hardware engineering the way it’s already transforming software.

Our client, backed by top-tier VCs + Google DeepMind's Jeff Dean, are building the simulations (RL environments) for foundation model labs (OpenAI, Anthropic, DeepMind), so agents can learn to design and verify chip IP. Their data distillation copilot, powered by 20+ frontier data generation and curation algorithms, can transform any hardware IP into a full RL environment where LLMs can learn to design and verify chips. This makes them the fastest and most scalable data company in the world for complex, in-demand engineering domains (7× faster than traditional data vendors).

About our client

• Building the hardware infrastructure that powers frontier AI agents—designing end-to-end systems that merge digital logic, verification, and data-driven complexity.
• Early-stage, high-growth venture backed company with global ambition and a mission to redefine how hardware meets AI.
• Seed funding, 5.3M, $1M contracts already signed, set to achieve Series A next year.

Key responsibilities

• Define and build the RL environment, product catalog, including scope, difficulty, and learning objectives for agents for each semiconductor environment (e.g., AXI, DMA, specialized modules - e.g. matrix multiplier core in AI accelerators)
• Define realistic tasks for agents to learn within each environment to automate hardware engineering
• Manage a team to execute the design and verification of each module and SoC and their agent tasks
• Collaborate with frontier AI researchers from labs like OpenAI and Anthropic to make sure the expected behavior is learned for useful hardware engineering automation
• Excitement and urgency around a ground breaking start up!

We’re looking for someone who

• Has 4–10+ years of RTL design or verification experience using System Verilog and industry-standard flows.
• Has strong debugging, scripting (Python/TCL) and automation skills.
• Will thrive in a fast-moving, high-impact startup environment with minimal process and high technical stakes.
• Is excited by the idea of joining a founding engineering team—helping build the function, not just join it.
• Is comfortable collaborating globally and working across silos (hardware, verification, software/agents).

Why this is a standout opportunity

• Work on bleeding-edge hardware at the intersection of AI + silicon design—this isn’t just another ASIC job.
• High visibility: your work will directly influence the product roadmap and company success.
• Competitive compensation + startup equity upside.

DOE: 180k-250k+ (flexibility)

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Software Development, IT System Custom Software Development, and Computer Hardware Manufacturing

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