ASIC/RTL Design Engineer

TPI Global Solutions; San Jose (CA); On-site; USD 180,000 - 300,000; Full time

Job summary

TPI Global Solutions in San Jose, CA, is seeking a Senior/Staff ASIC/RTL Design Engineer with 10+ years of industry experience to own end-to-end SoC development.

The role requires hands-on RTL coding, micro-architecture, and leadership across ASIC design flow, verification, timing closure, and silicon bring-up, with familiarity in ARM cores and high-speed interfaces such as PCIe, DDR5, Ethernet, DMA, and SATA.

Qualifications

• 10+ years of ASIC/RTL/SoC Design experience.
• SoC architecture and micro-architecture development.
• Experience with complete ASIC design flow.
• Synthesis and timing closure.
• Experience with ARM cores.
• Knowledge of high-speed interfaces such as: PCIe, DDR/DDR4/DDR5, Ethernet, DMA, SATA.
• Experience working with physical design, software, emulation, and silicon bring-up teams.

Skills

RTL design

Micro-architecture

ASIC design flow

Verification

Debug

Synthesis

Timing closure

ARM cores

PCIe

DDR5

Ethernet

DMA

SATA

Lead complex digital designs

Job description

This is a Senior/Staff-level ASIC/RTL Design Engineer role requiring 10+ years of industry experience in end-to-end SoC design. The strongest candidates should have hands-on expertise in RTL coding, micro-architecture, ASIC design flow, verification/debug, synthesis, timing closure, and silicon bring-up, with experience leading complex digital designs.

Core requirements:

• 10+ years of ASIC/RTL/SoC Design experience.
• SoC architecture and micro-architecture development.
• Experience with complete ASIC design flow.
• Synthesis and timing closure.
• Experience with ARM cores.
• Knowledge of high-speed interfaces such as: PCIe, DDR/DDR4/DDR5, Ethernet, DMA, SATA.
• Experience working with physical design, software, emulation, and silicon bring-up teams.