RTL Design Engineer

Diverse Lynx; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Diverse Lynx, LLC seeks an experienced hardware/ASIC engineer to join our design team in Austin. You will work on high-throughput, low-latency data transport ASIC/SOC projects, focusing on RTL coding (Verilog/SystemVerilog) and digital design for complex networks. Must have 9+ years of related engineering experience or a relevant advanced degree with years of experience.

Excellent communication required. Ideal candidates have track records in ASIC tapeouts, sub-micron tech, and familiarity with

Qualifications

• 9+ years of related technical engineering experience or equivalent degree with significant experience.
• 8+ years delivering IP/ASIC/SoC designs for arbitration and fabric logics.
• 8+ years in Digital Design with RTL coding in Verilog/SystemVerilog and related flows.
• Track record of successful ASIC tapeouts in deep sub-micron technologies.
• Excellent communication skills and ability to collaborate effectively.

Skills

9+ years of related technical eng. exp

8+ years delivering IP/ASIC/SoC

8+ years in Digital Design: Verilog /

ASIC tapeouts in deep sub-micron tech

Excellent communication skills

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

• 9+ years of related technical engineering experience
• OR bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
• 8+ years expertise in Digital Design including RTL coding in Verilog/System Verilog, RTL2PD tool/flow setup/maintenance/debug: Lint/CDC/RDC/VCLP/Synthesis/Timing constraints/FEV

Additional Or Preferred Qualifications

• 15+ years technical engineering experience
• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
• Track record of successful ASIC tape outs in deep sub-micron technologies
• Deep understanding of the physical design impact for each micro-architecture and work closely with PD engineers to find the best tradeoff given the performance/area/power constraints.
• Experienced on a variety of micro-architecture areas such as Complex Control Paths, Memory hierarchies and standard industry interfaces such as Advanced extensible Interface (AXI).
• 5+ years of experience in designing complex control logics on Network-On-Chip ASICs
• Excellent communication skills and ability to facilitate collaboration.