RISC-V CPU Power & Clock Design Engineer

SiFive; Boston (MA); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Flexible paid time off

Health benefits

401(k) plan

Employee stock option program

Job summary

A leading tech company in Boston is looking for a hardware engineer to design industry-leading CPU and interconnect IP for RISC-V adoption. Responsibilities include architecting power management solutions, collaborating with verification teams, and implementing design strategies. Ideal candidates have 3+ years of experience in CPU designs, proficiency in Verilog/SystemVerilog, and a team-oriented mindset. The position offers flexible paid time off, health benefits, and other competitive perks.

Qualifications

• 3+ years of experience in CPU and SoC clocking, reset, and power-management logic designs.
• Proficiency with Verilog, SystemVerilog, or VHDL.
• Background in successful CPU or SoC development from architecture through tapeout.

Responsibilities

• Work with architecture team to understand power management requirements.
• Design clocking, reset, and power management solutions.
• Perform sandbox verification and collaborate on verification plans.

Skills

CPU design

SoC architecture

Power management

Verilog/SystemVerilog

Attention to detail

Team-oriented mindset

Education

BS/MS degree in EE, CE, CS or related field

Tools

Git/Github

Jira

Confluence

Job description

A leading tech company in Boston is looking for a hardware engineer to design industry-leading CPU and interconnect IP for RISC-V adoption. Responsibilities include architecting power management solutions, collaborating with verification teams, and implementing design strategies. Ideal candidates have 3+ years of experience in CPU designs, proficiency in Verilog/SystemVerilog, and a team-oriented mindset. The position offers flexible paid time off, health benefits, and other competitive perks.