RISC-V CPU Power & Clock Design Engineer

SiFive; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Flexible paid time off

Health, vision and dental benefits

401(k) plan

Employee stock option program

Job summary

A pioneering tech company in Austin, Texas, is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer. This role involves designing industry-leading CPU cores and subsystems focused on RISC-V technology. The ideal candidate will have over 3 years of experience in CPU designs, proficiency in hardware design with Verilog/SystemVerilog, and a collaborative mindset. The position includes a competitive pay package and benefits like health insurance and flexible time off.

Qualifications

• 3+ years of experience in CPU and SoC designs.
• Expertise in power management logic designs.
• Proficiency with hardware (RTL) design.

Responsibilities

• Define power management requirements with the architecture team.
• Design core clocking, reset and power management solutions.
• Collaborate with verification and physical implementation teams.

Skills

CPU and SoC clocking design

Power management

Attention to detail

Team-oriented mindset

Education

BS/MS in EE, CE, CS or related

Tools

Verilog/SystemVerilog

Git/Github

Jira

Confluence

Job description

A pioneering tech company in Austin, Texas, is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer. This role involves designing industry-leading CPU cores and subsystems focused on RISC-V technology. The ideal candidate will have over 3 years of experience in CPU designs, proficiency in hardware design with Verilog/SystemVerilog, and a collaborative mindset. The position includes a competitive pay package and benefits like health insurance and flexible time off.