RFIC Layout Engineer

Apple; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

Apple in Austin, TX is seeking an experienced RFIC Layout Engineer to design and bring up next-generation wireless CMOS radios. You will perform transistor-level layout for RF and analog blocks, work through full verification, and collaborate on floorplanning and robust layout practices in a FinFET environment.

Ideal candidates have 10+ years of industry experience, strong FinFET expertise, and proficiency with Cadence tools and Calibre for DRC/LVS/ERC checks.

Qualifications

• BS in Electrical Engineering with 10+ years of relevant industry experience.

Responsibilities

• Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
• Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
• Co-work with designers on block level floorplanning.
• Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Skills

RF layout

Analog layout

LNA design

PLL design

Modulators design

Power amplifier design

ADC/DAC design

Baseband filters

Perl scripting

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence layout tools

Calibre DRC/ERC/LVS

Job description

Summary

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references.

Description

As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.

Key Responsibilities

• Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
• Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
• Co-work with designers on block level floorplanning.
• Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.
• FinFet experience.

Preferred Qualifications

• Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
• Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
• Solid understanding of RC delay, electromigration, and coupling.
• Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE.
• High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.
• Knowledge of CADENCE layout tools.
• Excellent communication skills.
• Scripting skills in PERL or SKILL.