RFIC Layout Engineer

Apple, Inc.; Austin (TX); On-site; USD 160,000 - 230,000; Full time

Job summary

Apple, Inc. in Austin, TX is seeking an RFIC Layout Engineer to design and bring up the next generation of wireless CMOS radios.

You will perform transistor-level layout of RF and analog blocks and drive the full verification flow from extraction to DFM, collaborating with design teams on floorplanning and guard-ring strategies. Ideal candidates have a BS with 10+ years of RF/analog layout experience, deep knowledge of RC delay, electromigration, high-frequency routing, and proficiency with

Qualifications

• BS degree with 10+ years of RF/analog layout experience.

Responsibilities

• Detailed transistor-level layout of RF/analog blocks (LNA, mixers, PLL, LO generation, modulators, PA, ADC/DAC).
• Layout flow through extraction, DRC, LVS, DFM checks.
• Collaborate on block-level floorplanning with designers.
• Review layout for power/ground routing, electromigration, signal integrity.

Skills

RF layout

Analog layout

Submicron CMOS

Parasitics minimization

Cadence tools

Scripting PERL/SKILL

Education

BS with 10+ years RF/analog layout experience

Tools

Cadence

Job description

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references.

Description

As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.

Responsibilities

• Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
• Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
• Co-work with designers on block level floorplanning.
• Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.

Preferred Qualifications

• Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
• Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
• Solid understanding of RC delay, electromigration, and coupling.
• Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE.
• High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.
• Knowledge of CADENCE layout tools.
• Scripting skills in PERL or SKILL.

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