RFIC AMS Verification Engineer - Build Starlink ICs

SpaceX; United States; On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical, vision, dental coverage

Paid parental leave

Vacation time and holidays

Job summary

SpaceX is seeking an AMS Verification Engineer to join the silicon engineering team. You will develop verification flows for full-chip RFICs/RF-SoCs and collaborate with cross-disciplinary teams to push the performance of Starlink hardware.

The role requires hands-on experience with SystemVerilog, UVM, Python, and Verilog-A/AMS, plus a strong foundation in analog/mixed-signal design and RF concepts. SpaceX offers competitive compensation and benefits.

Qualifications

• Bachelor's degree in engineering required.
• 1+ years of IC design/verification experience.
• Master's or PhD preferred in IC design/verification.
• Experience with AMS tools and flows.
• Experience with SystemVerilog, UVM, Python.
• Experience writing behavioral models in Verilog-A/AMS.
• Understanding of analog circuit fundamentals and RF/IPs.
• RTL and gate-level netlist knowledge.
• Willingness to work long hours and weekends.

Responsibilities

• Develop and own analog-on-top and digital-on-top verification flows for full-chip simulations of in-house RFICs and RF-SoCs.
• Create testbenches and flows to simulate critical interfaces between RFICs/SoCs.
• Collaborate with designers to improve speed and accuracy of simulations for advanced mixed-signal IPs (PLLs, DACs, ADCs).
• Develop behavioral models of RF/analog/mixed-mode circuit blocks and use these models in chip verification.
• Coordinate with ATE test engineering to develop and prototype test plans.
• Set up and run EM/IR simulations.

Skills

SystemVerilog

UVM

Python

AMS simulation

Verilog-A

Education

Bachelor's degree in engineering

Master's degree in engineering

PhD in engineering

Tools

AMS tools

Job description

SpaceX is seeking an AMS Verification Engineer to join the silicon engineering team. You will develop verification flows for full-chip RFICs/RF-SoCs and collaborate with cross-disciplinary teams to push the performance of Starlink hardware.

The role requires hands-on experience with SystemVerilog, UVM, Python, and Verilog-A/AMS, plus a strong foundation in analog/mixed-signal design and RF concepts. SpaceX offers competitive compensation and benefits.