AMS Verification Engineer - RFICs & Mixed-Signal

SpaceX; Redmond (WA); On-site; USD 125,000 - 200,000; Full time

Benefits offered by this job

Stock options

Health insurance

401(k)

Paid vacation

Paid holidays

Shuttle service

Job summary

SpaceX in Redmond, WA is hiring an AMS Verification Engineer (Silicon Engineering) to develop and own verification flows for RFICs and RF-SoCs, collaborating with systems, firmware, and ASIC teams.

The role requires a Bachelor’s in engineering and 1+ years in IC design/verification; preferred advanced degrees and experience with System-Verilog, UVM, Python, and AMS tools to model analog/mixed-signal IPs and ensure robust full-chip verification.

Qualifications

• Bachelor’s degree in an engineering discipline.
• 1+ years of IC design/verification experience.
• Experience with AMS simulation tools and flows is preferred.

Responsibilities

• Develop and own analog-on-top and digital-on-top verification flows for full-chip simulations.
• Create testbenches to simulate interfaces between RFICs/SoCs.
• Improve speed/accuracy of simulations for mixed-signal IPs like PLLs, DACs, ADCs.
• Develop behavioral models for analog/mixed-mode blocks and use in verification.
• Collaborate with ATE to develop and prototype test plans.
• Set up and run EM/IR simulations.

Skills

RF/Analog verification

SystemVerilog

UVM

Python

AMS verification flows

Gate-level simulation

Verilog-A/AMS

Digital/analog IPs

Education

Bachelor’s degree in engineering

Master’s or PhD preferred

Tools

AMS tools

Annotated gate-level sim

System-Verilog

UVM

Python

Job description

SpaceX in Redmond, WA is hiring an AMS Verification Engineer (Silicon Engineering) to develop and own verification flows for RFICs and RF-SoCs, collaborating with systems, firmware, and ASIC teams.

The role requires a Bachelor’s in engineering and 1+ years in IC design/verification; preferred advanced degrees and experience with System-Verilog, UVM, Python, and AMS tools to model analog/mixed-signal IPs and ensure robust full-chip verification.