AMS Verification Engineer: RFIC & Mixed‑Signal

SPACE EXPLORATION TECHNOLOGIES CORP; Redmond (WA); On-site; USD 125,000 - 200,000; Full time

Benefits offered by this job

Stock incentives

401(k) retirement plan

Paid vacation

Paid holidays

Shuttle service

Job summary

SpaceX in Redmond, WA is seeking an AMS Verification Engineer to develop verification flows for full‑chip RFICs and RF‑SoCs, focusing on analog‑on‑top and digital‑on‑top techniques. You will collaborate with cross‑disciplinary teams to model, simulate, and verify complex mixed‑signal IPs.

The role requires a Bachelor's in engineering and 1+ years in IC design/verification, with expertise in SystemVerilog, UVM, Python, and AMS tools.

Qualifications

• Bachelor’s degree in an engineering discipline
• 1+ years of research and/or industry experience in IC design/verification
• Experience with AMS simulation tools and flows
• Experience with annotated gate-level simulation within an AMS simulator
• Experience in SystemVerilog, UVM, Python
• Experience in writing behavioral models for analog/mixed‑mode IPs in Verilog‑A/AMS

Responsibilities

• Develop and own analog‑on‑top and digital‑on‑top design verification flows for full‑chip simulations of in‑house RFICs and RF‑SoCs
• Develop testbenches and flows to simulate critical interfaces between RFICs/SoCs
• Work with designers to improve speed/accuracy of simulations for advanced mixed‑signal IPs (PLLs, DACs, ADCs, etc.)
• Work with designers to create behavioral models of RF/analog/mixed‑mode circuit blocks, and employ these models in chip verification
• Work with ATE test engineering team to develop and prototype testplans
• Setup and run EM/IR simulations

Skills

SystemVerilog

UVM

Python

AMS simulation

Verilog-AMS

Gate-level sims

Analog modeling

RFIC design

RTL familiarity

Education

Bachelor’s degree in engineering

Tools

AMS simulator

EM/IR simulations

Job description

SpaceX in Redmond, WA is seeking an AMS Verification Engineer to develop verification flows for full‑chip RFICs and RF‑SoCs, focusing on analog‑on‑top and digital‑on‑top techniques. You will collaborate with cross‑disciplinary teams to model, simulate, and verify complex mixed‑signal IPs.

The role requires a Bachelor's in engineering and 1+ years in IC design/verification, with expertise in SystemVerilog, UVM, Python, and AMS tools.