AMS RFIC Verification Engineer - Analog/Mixed-Signal

InvestedintheMission; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock incentives

Health, vision and dental coverage

401(k) retirement plan

Paid vacation and holidays

Parental leave

Job summary

SpaceX is seeking an AMS Verification Engineer to join the Silicon Engineering team. You will develop verification flows for full‑chip simulations of in‑house RFICs and RF‑SoCs, and collaborate with cross‑disciplinary teams to push the performance of Starlink hardware.

The role requires a bachelor’s in engineering with 1+ years in IC design/verification, and preferred expertise in AMS simulations, SystemVerilog/UVM, Python, and Verilog‑A/AMS for analog/mixed‑signal IPs.

Qualifications

• Bachelor’s degree in engineering required; 1+ years IC design/verification experience.
• Experience with AMS simulation tools and flows preferred.
• Proficiency in SystemVerilog, UVM, Python and Verilog‑A/AMS for analog/mixed‑signal IPs.

Responsibilities

• Develop and own analog‑on‑top and digital‑on‑top verification flows for full‑chip simulations of in‑house RFICs and RF‑SoCs.
• Create testbenches and flows to simulate critical interfaces between RFICs/SoCs.
• Improve speed and accuracy of simulations for mixed‑signal IPs (PLLs, DACs, ADCs, etc.).
• Develop behavioral models and use them in chip verification.
• Coordinate with ATE test engineering to develop and prototype test plans.
• Setup and run EM/IR simulations.

Skills

AMS verification

SystemVerilog

UVM

Python

Gate-level simulation

Cross-disciplinary collaboration

Education

Bachelor’s degree in engineering

Master’s or PhD in engineering

Tools

AMS simulator

Verilog-A/AMS

RTL understanding

Job description

SpaceX is seeking an AMS Verification Engineer to join the Silicon Engineering team. You will develop verification flows for full‑chip simulations of in‑house RFICs and RF‑SoCs, and collaborate with cross‑disciplinary teams to push the performance of Starlink hardware.

The role requires a bachelor’s in engineering with 1+ years in IC design/verification, and preferred expertise in AMS simulations, SystemVerilog/UVM, Python, and Verilog‑A/AMS for analog/mixed‑signal IPs.