Research Fellow, Gen-AI & In-Memory Computing

National University of Singapore; Kent, Northern (WA, KY); Hybrid; USD 55,000 - 78,000; Full time

Job summary

National University of Singapore invites a Research Fellow to join the OUTSMART Corp Lab led by Professor Massimo Alioto. The role focuses on circuit exploration for near-PCM and in-memory SRAM computing macros, with hands-on validation of computing and memory macros and dataflow adaptation.

The successful candidate will validate test structures, chiplet interfaces, and final testchips across single and multi-chiplet arrangements, and will author high-quality research papers for leading

Qualifications

• The candidate must hold a PhD in Electrical Engineering or a closely related field.
• Expertise in circuit architectures and transistor‑level design is required.
• Knowledge of silicon chip design and EDA tools is essential.
• Ability to work independently and collaboratively in a team.
• Strong communication and interpersonal skills.
• Open to fixed term contract.

Responsibilities

• Explore circuit implementations for near-PCM and in-memory SRAM computing macros.
• Experimentally validate computing and memory macros and support for similarity-based computation skipping.
• Validate test structures with dataflow adaptation in single and multi-chiplet configurations.
• Validate chiplet interfaces, synchronization, and final memory-logic aggregation.
• Publish high-quality research papers and present findings at international conferences.
• Guide PhD and master's students and track technical milestones.

Skills

Circuit architectures

Transistor-level design

Independent work

Communication skills

Education

PhD in EE or related

Tools

EDA tools

Job description

National University of Singapore invites a Research Fellow to join the OUTSMART Corp Lab led by Professor Massimo Alioto. The role focuses on circuit exploration for near-PCM and in-memory SRAM computing macros, with hands-on validation of computing and memory macros and dataflow adaptation.

The successful candidate will validate test structures, chiplet interfaces, and final testchips across single and multi-chiplet arrangements, and will author high-quality research papers for leading