Research Fellow (Gen-AI)

National University of Singapore; Kent, Northern (WA, KY); Hybrid; USD 55,000 - 78,000; Full time

Job summary

National University of Singapore invites a Research Fellow to join the OUTSMART Corp Lab led by Professor Massimo Alioto. The role focuses on circuit exploration for near-PCM and in-memory SRAM computing macros, with hands-on validation of computing and memory macros and dataflow adaptation.

The successful candidate will validate test structures, chiplet interfaces, and final testchips across single and multi-chiplet arrangements, and will author high-quality research papers for leading

Qualifications

• The candidate must hold a PhD in Electrical Engineering or a closely related field.
• Expertise in circuit architectures and transistor‑level design is required.
• Knowledge of silicon chip design and EDA tools is essential.
• Ability to work independently and collaboratively in a team.
• Strong communication and interpersonal skills.
• Open to fixed term contract.

Responsibilities

• Explore circuit implementations for near-PCM and in-memory SRAM computing macros.
• Experimentally validate computing and memory macros and support for similarity-based computation skipping.
• Validate test structures with dataflow adaptation in single and multi-chiplet configurations.
• Validate chiplet interfaces, synchronization, and final memory-logic aggregation.
• Publish high-quality research papers and present findings at international conferences.
• Guide PhD and master's students and track technical milestones.

Skills

Circuit architectures

Transistor-level design

Independent work

Communication skills

Education

PhD in EE or related

Tools

EDA tools

Job description

We are looking for a Research Fellow for the OUTSMART Corp Lab led by Professor Massimo Alioto, at the Department of Electrical and Computer Engineering, National University of Singapore (NUS).

The selected candidate is expected to:

• circuit exploration of near-PCM and in-memory SRAM computing macros, and related models
• experimental validation of computing and memory macros and their support of similarity/confidence-based computation skipping, and dataflow adaptation
• experimental validation of test structures with dataflow adaptation in single chip, high memory-logic interspersion
• experimental validation of chiplet interfaces and synchronization, test structures with final memory-logic aggregation, and dataflow adaptation across chiplets
• experimental validation of final testchip in single- and many-chiplet arrangement
• experimental validation of final testchip in single-chiplet arrangement
• authoring high-quality research papers for leading conferences and journals and presenting findings at international conferences.
• managing technical milestones for the project and providing technical guidance to PhD and master’s students within the group.

The appointment can commence immediately with a 1-year contract, with prospect of extension. Salary will be commensurate with qualifications and experience.

Qualifications

The candidate must possess:

• a PhD degree in either Electrical Engineering or strictly related (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• open to fixed term contract.