DRAM Architecture Intern — AI-Driven Research Lab

Micron Technology, Inc.

San Jose, Northern (CA, KY)

Hybrid

USD 96,000 - 116,000

Full time

2 days ago
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Job summary

Micron Technology, Inc. in San Jose, CA, is seeking an Intern in DRAM Architecture to develop software frameworks, automate experiments, and apply AI-assisted workflows to memory research.

You will collaborate with architects and researchers to evaluate emerging memory technologies and build simulation environments. The role emphasizes performance, power, bandwidth and workload analyses, with opportunities to contribute to future memory technology strategies.

Qualifications

  • Pursuing a Master’s or PhD in Computer Engineering, Electrical Engineering, or CS.
  • Experience in Python, C++, or similar languages.
  • Familiarity with memory architectures and modeling/simulation.
  • Experience with AI-enabled tools and generative AI platforms.
  • Strong analytical, communication and collaboration skills.

Responsibilities

  • Develop software frameworks, simulation environments, and automation tools for DRAM architecture research.
  • Design AI-assisted workflows for simulation generation and data analysis.
  • Analyze memory architectures (DRAM/LPDDR/DDR6/MRDIMM/CAMM) using modeling and simulation techniques.
  • Perform performance, power, bandwidth, latency, and workload characterization.
  • Collaborate with architects and researchers to document methodologies and present findings.

Skills

Python
C++
AI workflows

Education

Master's or PhD in Computer Engineering/ Electrical Engineering/ CS

Tools

Simulation software

Job description

Micron Technology, Inc. in San Jose, CA, is seeking an Intern in DRAM Architecture to develop software frameworks, automate experiments, and apply AI-assisted workflows to memory research.

You will collaborate with architects and researchers to evaluate emerging memory technologies and build simulation environments. The role emphasizes performance, power, bandwidth and workload analyses, with opportunities to contribute to future memory technology strategies.

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