Midcore Design Verification Engineer

Tenstorrent; Santa Clara (CA); Remote; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify high‑performance RISC‑V CPU cores. You will collaborate with architects, RTL designers, and software engineers to develop verification strategies, build test benches, and drive issue closure in a hands‑on role.

The position is remote, open to candidates in North America or Spain, with offers aligned to level and experience. Strong SystemVerilog/UVM and C/C++ or Python skills are required, along with 6+ years in CPU

Qualifications

• 6+ years in design verification for CPUs/SoCs/ASICs.
• Strong SystemVerilog and UVM experience with testbenches.
• Proficient in C/C++ or Python and collaboration with RTL teams.

Responsibilities

• Develop verification strategies and test plans for CPUs.
• Build robust test environments and testbenches.
• Uncover corner cases and debug failures in RTL simulations.
• Own portions of the verification effort and drive issues to closure.
• Work closely with CPU architects, RTL designers and software engineers.

Skills

Hands-on verification

Debugging

Root-cause analysis

Ownership of tasks

Cross-functional collaboration

CPU architecture understanding

Tools

SystemVerilog

UVM

Constrained-random testing

Waveform debugging

C/C++

Python

Job description

Tenstorrent is leading the industry on cutting‑edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Mid Core Design Verification Engineer to help verify the next generation of high-performance RISC‑V CPU cores.

You’ll work closely with CPU architects, RTL designers, and software engineers to develop verification strategies, build robust test environments, and uncover the corner cases that matter in a modern out‑of‑order processor. This is a hands‑on role where you’ll have the opportunity to own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands‑on verification engineer who enjoys understanding how CPUs work and finding the bugs others miss.
• Comfortable working across architecture, microarchitecture, RTL, and verification to understand complex CPU behavior.
• A strong problem solver who can debug failures, identify root causes, and work collaboratively toward solutions.
• Organized and self‑motivated, with the ability to take ownership of verification tasks while working effectively within a larger team.
• Curious about high‑performance processors, RISC‑V, and the challenges of verifying increasingly complex CPU designs.

What We Need

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including testbench development, constrained‑random testing, assertions, and functional coverage.
• Understanding of CPU architecture and/or microarchitecture, ideally including concepts such as pipelines, out‑of‑order execution, caches, load/store, branch prediction, or instruction scheduling.
• Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools.
• Strong C/C++ or Python skills and the ability to work effectively with RTL designers, architects, and other verification engineers.

What You Will Learn

• Gain deep hands‑on experience verifying high‑performance, out‑of‑order RISC‑V CPU cores.
• Learn how CPU microarchitecture decisions translate into RTL and how those designs are verified against architectural intent.
• Develop expertise in advanced verification techniques for complex processor pipelines and interacting subsystems.
• Work closely with CPU architects and RTL engineers to understand the full design lifecycle from specification through silicon.
• Build experience with the challenges of verifying next‑generation CPUs designed for AI, HPC, and high‑performance computing systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.