Sr. Verification Engineer (ASIC/SoC)

Varstaff Staffing; El Segundo (CA); Remote; USD 120,000 - 180,000; Full time

Job summary

Varstaff Staffing is seeking Senior Verification Engineers (ASIC/SoC) for a remote, US-wide 8+ month contract. You will own verification planning, select methods, and build environments for complex blocks and subsystems, spanning IP, subsystems and full SoC verification.

The role emphasizes constrained-random, formal and directed testing, with AI-assisted stimulus, regression triage and coverage analytics. Mentoring junior engineers is also expected.

Qualifications

• 7+ years of professional ASIC or SoC functional verification experience.
• Hands-on SystemVerilog, UVM or formal testbench development and maintenance.
• Metric-driven verification: planning, assertions and functional coverage closure.
• Verifying complex digital control and datapath logic, including RTL and system-level debug.

Responsibilities

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• Translate design specifications into verification strategies, measurable coverage goals and early identification of high-risk scenarios.
• Select the verification method for each problem: constrained-random simulation, formal analysis or directed testing.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components and assertions.
• Drive functional coverage closure, regression health and sign-off readiness across simulation and formal results.
• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem and SoC levels.
• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage and coverage analytics.
• Review testbench architecture and debug methodology, and mentor junior engineers.

Skills

SystemVerilog

UVM

Formal verification

RTL

Debug

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

Varstaff is hiring Senior Verification Engineers (ASIC/SoC), remote (US-wide), 8+ month contract

About the Job: Join the ASIC & Networking team of a leading commercial space company supporting its first in-house silicon program: a high-throughput modem and a DSP-intensive digital beamformer, with first tapeout targeted for 2027. Verification strategy, methodology and infrastructure are being defined now, and you will help define them. The work spans IP, subsystem and full SoC verification, including CPU subsystems, performance-critical interconnects, security, high-speed peripherals, modem datapath and PHY layers, DSP and beamforming compute, and mixed-signal interfaces. The team treats constrained-random simulation, formal methods and processor-driven SoC testing as equal first-class tools, and is building an AI-enabled verification platform (LLM-assisted stimulus and testbench generation, automated regression triage and failure clustering, data-driven coverage closure). Wireless, modem, baseband or DSP verification background is welcome but not required.

Location: Remote. Open to candidates anywhere in the US. If the contract converts to direct employment, you must be local to (or relocate to) one of the client sites in Southern California or Austin, TX. US citizenship required.

Key Responsibilities

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• Translate design specifications into verification strategies, measurable coverage goals and early identification of high-risk scenarios.
• Select the verification method for each problem: constrained-random simulation, formal analysis or directed testing.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components and assertions.
• Drive functional coverage closure, regression health and sign-off readiness across simulation and formal results.
• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem and SoC levels.
• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage and coverage analytics.
• Review testbench architecture and debug methodology, and mentor junior engineers.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering or a related field, or 7+ years of equivalent experience.
• 5+ years of professional ASIC or SoC functional verification experience.
• Hands-on SystemVerilog, UVM or formal testbench development and maintenance.
• Metric-driven verification: planning, assertions and functional coverage closure.
• Verifying complex digital control and datapath logic, including RTL and system-level debug.

Preferred Qualifications

• Space-based communications, wireless communications, or modem, baseband or DSP hardware background.
• Verifying LDPC, FEC, framing or beamforming logic using bit-accurate reference models and fixed-point analysis.
• Formal verification on production silicon (connectivity, register maps, arbitration, CDC or security properties).
• Interconnect or NoC verification (performance, bandwidth, QoS, deadlock analysis).
• Verifying fault tolerance and reliability features such as ECC, redundancy schemes or fault injection.
• C-based or portable stimulus for SoC, CPU boot and firmware-driven test scenarios.
• Applying AI, ML or LLM tooling to stimulus generation, regression triage or coverage analysis.