Remote Senior ASIC Lead & Design Engineer

Chelsea Search Group; Raleigh (NC); Remote; USD 180,000 - 280,000; Full time

Job summary

Chelsea Search Group is seeking an experienced ASIC Chip Lead and Design Engineer for a remote role. You will drive architectural design, RTL development, and physical design collaboration across the full ASIC/SoC lifecycle, delivering high-performance silicon with attention to power and area.

The ideal candidate has 10+ years in ASIC/SoC and strong Verilog/SystemVerilog skills, along with proficiency in Synopsys Design Compiler and other EDA tools.

Qualifications

• 10+ years of direct industry experience with ASIC and/or SoC design.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proficiency in RTL based digital IC design using Verilog/SystemVerilog.

Responsibilities

• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip’s components.
• Use Synopsys Design Compiler to create RTL designs and optimize for area, power, and performance.
• Coordinate with physical design teams for place-and-route and timing constraints.
• Verify processor conformance and optimize processor performance and power efficiency.
• Support verification engineers to ensure functional correctness and testbench development.

Skills

Digital design

Verilog/SystemVerilog

RTL design

C/C++

Unix/Linux

Education

BSEE/MSEE or equivalent

Tools

Synopsys Design Compiler

EDA tools

Job description

Chelsea Search Group is seeking an experienced ASIC Chip Lead and Design Engineer for a remote role. You will drive architectural design, RTL development, and physical design collaboration across the full ASIC/SoC lifecycle, delivering high-performance silicon with attention to power and area.

The ideal candidate has 10+ years in ASIC/SoC and strong Verilog/SystemVerilog skills, along with proficiency in Synopsys Design Compiler and other EDA tools.