Remote ASIC Lead & SoC Design Engineer

Chelsea Search Group; Chandler (AZ); Remote; USD 150,000 - 190,000; Full time

Job summary

Chelsea Search Group seeks an ASIC Chip Lead and Design Engineer (remote). You’ll design and deliver complex, custom ASICs from concept through silicon, collaborating with architecture, verification, physical design, applications, and business teams to turn requirements into high-performance silicon.

The role is hands-on across the full ASIC/SoC design lifecycle; radiation-hardened design, analog/mixed-signal, EDA methodologies, or standard-cell library work are a plus.

Qualifications

• BSEE/MSEE or equivalent degree required.
• 10+ years of ASIC/SoC design experience.
• Proficient in Synopsys Design Compiler and other EDA tools.
• Strong digital design fundamentals and RTL based design (Verilog/SystemVerilog).
• Familiar with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving and attention to detail.
• Leadership and mentoring abilities; self-starter.
• Able to collaborate across multi-site teams.

Responsibilities

• Lead architectural design of ASICs from high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality and interfaces.
• Develop detailed specifications for chip components.
• Use RTL/Design Compiler and optimize for area, power, and performance.
• Develop timing constraints and work with physical design on place-and-route.
• Constrain and verify RISC processors within the chip.
• Coordinate with verification and test teams; create testbenches.

Skills

ASIC/SoC design

RTL design

Verilog/SystemVerilog

C/C++/scripting

Mentorship

leadership

problem-solving

team collaboration

Education

BSEE/MSEE or equivalent

Tools

Synopsys Design Compiler

EDA tools

UNIX/Linux

Job description

Chelsea Search Group seeks an ASIC Chip Lead and Design Engineer (remote). You’ll design and deliver complex, custom ASICs from concept through silicon, collaborating with architecture, verification, physical design, applications, and business teams to turn requirements into high-performance silicon.

The role is hands-on across the full ASIC/SoC design lifecycle; radiation-hardened design, analog/mixed-signal, EDA methodologies, or standard-cell library work are a plus.