Lead ASIC Architect — RTL & SoC Design Expert

Chelsea Search Group; Minneapolis (MN); On-site; USD 150,000 - 230,000; Full time

Job summary

Chelsea Search Group in Minneapolis seeks an experienced ASIC Chip Lead and Design Engineer to drive architectural design of complex ASICs from concept to silicon. You will collaborate across architecture, verification, physical design, and business teams to achieve high-performance, power-efficient silicon while mentoring junior engineers.

The ideal candidate has 10+ years in ASIC/SoC design, strong RTL/Verilog expertise, and hands-on experience with Synopsys Design Compiler and EDA flows.

Qualifications

• BSEE/MSEE or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A strong background in RTL based digital IC design using Verilog/SystemVerilog.
• Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to mentor junior engineers.
• Experience with industry standard development tools and methodologies.

Responsibilities

• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip’s components.
• Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
• Optimize RTL code for area, power, and performance.
• Implement and verify complex digital blocks.
• Develop timing constraints for the entire chip.
• Work closely with physical design teams to ensure successful place-and-route.
• Constrain and verify RISC processors within the chip.
• Optimize processor performance and power efficiency.
• Collaborate with physical design teams on floorplanning, placement, and routing.
• Address any design closure issues.
• Work with verification engineers to ensure functional correctness.
• Assist in creating testbenches and verifying the chip’s functionality.
• Modern revision-control tools and best-practices in a collaborative, multi-site design community.

Skills

RTL design

Verilog/SystemVerilog

C/C++

Python/TCL scripting

UNIX/Linux

Mentoring

Leadership

Problem solving

Team collaboration

Education

BSEE/MSEE or equivalent

Tools

Synopsys Design Compiler

Job description

Chelsea Search Group in Minneapolis seeks an experienced ASIC Chip Lead and Design Engineer to drive architectural design of complex ASICs from concept to silicon. You will collaborate across architecture, verification, physical design, and business teams to achieve high-performance, power-efficient silicon while mentoring junior engineers.

The ideal candidate has 10+ years in ASIC/SoC design, strong RTL/Verilog expertise, and hands-on experience with Synopsys Design Compiler and EDA flows.