Remote ASIC Design Lead - RTL/SoC & PPA Expert

Chelsea Search Group; San Diego (CA); Remote; USD 180,000 - 260,000; Full time

Job summary

Chelsea Search Group is seeking an ASIC Chip Lead and Design Engineer to design and deliver complex ASICs from concept through silicon in a remote role. You’ll collaborate across architecture, verification, physical design, and business teams to translate demanding requirements into high‑performance silicon with optimized power, performance, and area.

The ideal candidate will have 10+ years in ASIC/SoC design, deep RTL experience in Verilog/SystemVerilog, and proficiency with Synopsys Design

Qualifications

• Bachelor's degree in electrical engineering or equivalent.
• 10+ years of direct industry experience with ASIC/SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem‑solving skills and attention to detail.
• Strong RTL based digital IC design using Verilog/SystemVerilog.
• Proven track record of first‑pass successes.
• Self‑starter with ability to assume leadership roles.
• Ability to mentor junior engineers and work in a diverse team.

Responsibilities

• Lead architectural design of ASICs based on high‑level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for chip components.
• Use Synopsys Design Compiler to create RTL designs and optimize for area, power, and performance.
• Develop timing constraints and collaborate with physical design teams for place‑and‑route.
• Constrain and verify RISC processors within the chip and optimize performance.
• Work with verification engineers to ensure functional correctness and create testbenches.
• Collaborate on floorplanning, placement, and routing; address design closure issues.
• Contribute to internal design methodologies and processes.

Skills

Verilog/SystemVerilog

Leadership

Mentoring

Problem solving

RTL design

Digital design principles

Scripting (Python/TCL)

RISC architectures

Team collaboration

Education

BSEE/MSEE or equivalent

Tools

Synopsys Design Compiler

EDA tools

UNIX/Linux scripting

Job description

Chelsea Search Group is seeking an ASIC Chip Lead and Design Engineer to design and deliver complex ASICs from concept through silicon in a remote role. You’ll collaborate across architecture, verification, physical design, and business teams to translate demanding requirements into high‑performance silicon with optimized power, performance, and area.

The ideal candidate will have 10+ years in ASIC/SoC design, deep RTL experience in Verilog/SystemVerilog, and proficiency with Synopsys Design