Remote Senior ASIC Design Engineer — AI & HPC Networking

cornelisnetworks; Austin (TX); Remote; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity

Performance bonus

Health insurance

401(k) match

Open Time Off

Paid holidays

Disability insurance

Life insurance

Pet insurance

Job summary

Cornelis Networks is seeking Senior ASIC Design Engineers to advance high‑performance SoCs for AI interconnects and HPC workloads. You will design RTL in Verilog/SystemVerilog, collaborate with verification and physical design teams, and help optimize timing and power for 50G/100G/400G Ethernet paths.

Join a fast‑growing, remote‑friendly team with equity, competitive compensation, and a broad benefits package.

Qualifications

• 8+ years of post-college experience in digital design with proficiency in Verilog and SystemVerilog.
• Experience in RTL design for high-speed data paths or packet processing in ASICs.
• Deep understanding of Host Ethernet adaptor architectures.
• Familiarity with timing closure and modern physical design methodologies.
• Proven ability in system-level debug and root cause analysis of technical issues.

Responsibilities

• Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic.
• Collaborate with verification engineers to create block-and system-level test plans to ensure comprehensive design coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.

Skills

Verilog

SystemVerilog

Digital design

RTL design

Ethernet host adapters

Timing closure

Debugging

Communication skills

Education

B.S. in CE

M.S. in EE

Tools

Design Compiler

Spyglass

PrimeTime

Job description

Cornelis Networks is seeking Senior ASIC Design Engineers to advance high‑performance SoCs for AI interconnects and HPC workloads. You will design RTL in Verilog/SystemVerilog, collaborate with verification and physical design teams, and help optimize timing and power for 50G/100G/400G Ethernet paths.

Join a fast‑growing, remote‑friendly team with equity, competitive compensation, and a broad benefits package.