Senior Analog Design Engineer – High-Performance ICs

TylSemi, Inc.; San Jose (CA); On-site; USD 130,000 - 210,000; Full time

Job summary

TylSemi, Inc. in San Jose, CA is seeking a Principal Analog Design Engineer to design high-performance analog and mixed-signal circuits for a scalable silicon infrastructure.

The role spans a wide experience range (5–30 years) and requires translating system needs into silicon-ready designs, validating performance across corners, and partnering with layout, verification, test, and product teams to drive first-time-right outcomes.

Qualifications

• 5+ years of experience in analog or mixed-signal IC design.
• Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems.
• Proficiency with industry-standard EDA tools and simulation flows.
• Experience closing designs through post-layout parasitics and across PVT corners.
• Ability to translate ambiguous system needs into clear block requirements.
• Strong debugging skills and clear communication in cross-functional environments.

Responsibilities

• Own end-to-end analog block development: requirements, architecture, transistor-level design, verification.
• Design and optimize analog/mixed-signal circuits such as amplifiers, references, biasing, regulators, comparators, oscillators, data converters.
• Drive performance across PVT corners and consider aging/reliability in design.
• Collaborate with layout for floorplanning, matching, parasitics-aware design, and post-layout closure.
• Develop/testbenches, modeling collateral, and documentation for verification and integration.
• Support silicon bring-up, debug, and ECO implementation.
• Contribute to design methodology improvements and scalable best practices.

Skills

Analog design

Mixed-signal

EDA tools

Post-layout parasitics

Debugging

Clear communication

Job description

TylSemi, Inc. in San Jose, CA is seeking a Principal Analog Design Engineer to design high-performance analog and mixed-signal circuits for a scalable silicon infrastructure.

The role spans a wide experience range (5–30 years) and requires translating system needs into silicon-ready designs, validating performance across corners, and partnering with layout, verification, test, and product teams to drive first-time-right outcomes.