Remote FPGA Prototyping Intern — Hardware Accelerator

Ludwig Computing, Inc.; Mill Valley, Northern (CA, KY); Hybrid; USD 28,000 - 48,000; Full time

Job summary

Ludwig Computing, Mill Valley, CA, is seeking an Hardware Engineer intern focused on FPGA-based prototyping and hardware bring-up. You will work with the founding team to implement and validate core logics and subsystems for custom compute hardware.

The internship emphasizes FPGA development, RTL/HLS-based design, and building experience across Vivado/Quartus/OpenCL flows, with opportunities to explore ASIC-relevant design concepts and system-level integration.

Qualifications

• Pursuing a degree in engineering (EE/CS)
• Experience with FPGA development and RTL/HLS design
• Familiarity with Vivado/Quartus or equivalent tooling
• Strong digital logic fundamentals and timing closure
• Experience with memory mapping on FPGA
• OpenCL or HLS targeting FPGA desirable
• Prior FPGA development boards experience beneficial
• System-level co-design and hardware/software integration exposure

Responsibilities

• Translate architectural concepts into FPGA prototypes
• Design and simulate custom processing modules using Verilog/VHDL/HLS
• Implement and validate processing components on FPGA with Vivado/Quartus/OpenCL flows
• Benchmark latency, area, throughput, memory bandwidth
• Build testbenches and assist with system integration
• Collaborate to define hardware/software boundaries and demos bring-up

Skills

FPGA development

RTL/HLs-based design

Verilog/SystemVerilog

Digital logic fundamentals

Memory mapping

Simulation/Debugging

System-level prototyping

Numerical computing

ASIC flows exposure

Education

Pursuing EE/CS degree

PhD/MS student in EE/CS

Tools

Vivado

Quartus

OpenCL

OpenCL-based flows

HLS

FPGA development boards

HDL

Job description

Ludwig Computing, Mill Valley, CA, is seeking an Hardware Engineer intern focused on FPGA-based prototyping and hardware bring-up. You will work with the founding team to implement and validate core logics and subsystems for custom compute hardware.

The internship emphasizes FPGA development, RTL/HLS-based design, and building experience across Vivado/Quartus/OpenCL flows, with opportunities to explore ASIC-relevant design concepts and system-level integration.