Senior FPGA R&D Engineer – HAPS Prototyping

Synopsys, Inc.; Sunnyvale (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Synopsys, Inc. in Sunnyvale, CA seeks a senior FPGA engineer to advance HAPS prototyping platforms. You will develop FPGA-optimized implementations, manage RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices.

You will lead multi-FPGA partitioning, clock distribution, and reset architectures while collaborating with hardware, software, and manufacturing teams to accelerate customer designs before silicon.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of hands-on FPGA and RTL design experience.
• Expert-level proficiency in SystemVerilog and Verilog for RTL design, with deep understanding of digital design fundamentals, clocking architectures, reset strategies, clock domain crossing, and timing analysis.
• Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including optimization for resource utilization, SLR crossings, and routing congestion.
• Strong programming skills in C/C++ and Python with a proven track record of developing production-quality software, automation frameworks, debug utilities, and engineering tools.
• Proficiency using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and multimeters to debug and validate hardware systems.
• Experience with signal integrity characterization, PRBS testing, eye diagram analysis, jitter measurement, and link margining is a strong plus.

Responsibilities

• Develop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges.
• Own the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices.
• Drive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues.
• Develop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins.
• Build and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures that work reliably across device boundaries.
• Debug RTL, timing, clocking, and integration issues across simulation, emulation, and physical hardware using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and spectrum analyzers.
• Collaborate with architecture, hardware, software, manufacturing, and verification teams to deliver prototyping solutions from concept through production deployment.

Skills

SystemVerilog

Verilog

RTL design

Clock domain crossing

Timing analysis

Vivado

AMD/Xilinx FPGA

C/C++

Python

Hardware bring-up

PRBS testing

Eye diagram analysis

Jitter measurement

Link margining

Lab equipment

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Vivado

Place-and-route

Timing closure

Oscilloscopes

Logic analyzers

Protocol analyzers

Multimeters

Job description

Synopsys, Inc. in Sunnyvale, CA seeks a senior FPGA engineer to advance HAPS prototyping platforms. You will develop FPGA-optimized implementations, manage RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices.

You will lead multi-FPGA partitioning, clock distribution, and reset architectures while collaborating with hardware, software, and manufacturing teams to accelerate customer designs before silicon.