FPGA Intern – Custom Compute Hardware

Ludwig Computing, Inc.; Mill Valley, Northern (CA, KY); Hybrid; USD 28,000 - 48,000; Full time

Job summary

Ludwig Computing, Mill Valley, CA, is seeking an Hardware Engineer intern focused on FPGA-based prototyping and hardware bring-up. You will work with the founding team to implement and validate core logics and subsystems for custom compute hardware.

The internship emphasizes FPGA development, RTL/HLS-based design, and building experience across Vivado/Quartus/OpenCL flows, with opportunities to explore ASIC-relevant design concepts and system-level integration.

Qualifications

• Pursuing a degree in engineering (EE/CS)
• Experience with FPGA development and RTL/HLS design
• Familiarity with Vivado/Quartus or equivalent tooling
• Strong digital logic fundamentals and timing closure
• Experience with memory mapping on FPGA
• OpenCL or HLS targeting FPGA desirable
• Prior FPGA development boards experience beneficial
• System-level co-design and hardware/software integration exposure

Responsibilities

• Translate architectural concepts into FPGA prototypes
• Design and simulate custom processing modules using Verilog/VHDL/HLS
• Implement and validate processing components on FPGA with Vivado/Quartus/OpenCL flows
• Benchmark latency, area, throughput, memory bandwidth
• Build testbenches and assist with system integration
• Collaborate to define hardware/software boundaries and demos bring-up

Skills

FPGA development

RTL/HLs-based design

Verilog/SystemVerilog

Digital logic fundamentals

Memory mapping

Simulation/Debugging

System-level prototyping

Numerical computing

ASIC flows exposure

Education

Pursuing EE/CS degree

PhD/MS student in EE/CS

Tools

Vivado

Quartus

OpenCL

OpenCL-based flows

HLS

FPGA development boards

HDL

Job description

Ludwig Computing FPGA Intern – Custom Compute Hardware Mill Valley, CA·Remote·Intern Company website Apply for FPGA Intern – Custom Compute Hardware

Internship primarily focused on FPGA-based prototyping and hardware bring-up

About Ludwig Computing

Harnessing Randomness, Accelerating Compute;Creating the Foundational Technology for the Future of Intelligent Compute

Description

About us:

At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvementsin energy efficiency and performance for various AI workloads. We are building a future where high performance computing is powered by leaner, smarter, and extremely efficient hardware and software platforms. Join us at the ground floor as we build the future of intelligent compute.

About the Role

We are looking for a technically exceptional and intellectually curious Hardware Engineer intern who is passionate about hardware acceleration and wants to work on cutting-edge compute platforms. You will work directly with the founding team to assist in implementing and validating core logics, processing algorithms, and other subsystems. This is a hands-on, research-meets-build role in developing custom blocks for advanced computational workloads. This internship is primarily focused on FPGA-based prototyping and hardware bring-up, with opportunities to explore ASIC-relevant design flows and system-level integration in support of broader architectural development. Candidates interested in system-level digital prototyping and early-stage accelerator development are encouraged to apply.

Responsibilities

• Translate architectural concepts into FPGA prototypes
• Design and simulatecustom processing modulesusingVerilog, VHDL, or high-level synthesis (HLS)
• Implement and validate processing components on FPGA platform using industry-standard tools (e.g.,Vivado,Quartus, orOpenCL-based flows)
• Benchmark performance and optimize tradeoffs inlatency, area, throughput, and memory bandwidth
• Build testbenches, run timing/area analysis, and assist with system integration
• Collaborate with the team to definehardware/software boundaries, and support bring-up of real demos.

Requirements

• Experience with FPGA development,RTL or HLS-based designin Verilog/SystemVerilog, VHDL, or C++
• Familiarity with FPGA development tools (Vivado, Quartus, or equivalent)
• Strong grasp ofdigital logic fundamentals, including pipelining and timing closure
• Experience withmemory mapping and hierarchyon FPGA.
• Strong skills in simulation, debugging, and synthesis workflows
• Currently pursuing a degree in engineering (preferably Electrical Engineering, Computer Science)
• Experience withOpenCL or HLS-based design targeting FPGA
• Prior Experience withFPGA development boards
• Familiarity withhardware/software co-design and system-level integration
• Course work or project experience in digital design, computer architecture, or embedded systems.
• Understanding ofmemory system tradeoffs
• Exposure tonumerical computing, orcustom arithmetic units
• Exposure toASIC design concepts, such as synthesis, floor planning, or RTL-to-GDS toolchains
• Familiarity withanalog or mixed-signal concepts
• Currently PhD/MS student in EE/CS

What You'll Gain

• Opportunity to work on next generation AI compute architectures
• Hands-on experience buildingnovel, high-speed, energy-efficient compute acceleratorson FPGAs
• Opportunity to build skills that bridge intoASIC flows, including RTL quality, test benching, and synthesis-readiness
• Mentorship from a team with expertise inhardware-software co-design, digital architecture, and early-stage prototyping