Remote CPU Physical Design Methodology Lead

Tenstorrent; Santa Clara, Northern (CA, KY); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a seasoned Physical Design CPU Methodology Engineer to define and drive the implementation methodology, automation strategy, and signoff infrastructure for high‑performance CPU cores across advanced nodes. You will lead RTL‑to‑GDS execution, optimize power and timing, and mentor teams across locations.

The role emphasizes building scalable PD flows, exploring AI/ML enabled tooling, and partnering with cross‑functional engineering groups to deliver predictable, high‑quality

Qualifications

• 10+ years of ASIC/SoC/CPU experience, ideally high‑performance CPUs or complex digital designs.
• Deep expertise across RTL‑to‑GDS implementation and signoff, including timing closure, power optimization, SI/EM/IR, extraction, and physical verification.
• Proven track record building or owning physical design methodology, automation, or CAD flows; strong scripting in Tcl, Python, or Perl.
• Technical leadership with cross‑team influence and ability to mentor engineers across distributed teams.

Responsibilities

• Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification.
• Explore AI/ML enabled PD tooling, begin synthesis and PnR of CPU partitions, and start developing the new program RM flow.
• Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows to improve predictability, turnaround time, and PPA.
• Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design.

Skills

RTL to GDS

Timing closure

Power optimization

Scripting (TclPython)

Leadership

Mentoring engineers

Tools

CAD flows

Job description

Tenstorrent is seeking a seasoned Physical Design CPU Methodology Engineer to define and drive the implementation methodology, automation strategy, and signoff infrastructure for high‑performance CPU cores across advanced nodes. You will lead RTL‑to‑GDS execution, optimize power and timing, and mentor teams across locations.

The role emphasizes building scalable PD flows, exploring AI/ML enabled tooling, and partnering with cross‑functional engineering groups to deliver predictable, high‑quality