Remote Analog/Mixed-Signal IC Layout Engineer (Contract)

Visibl Semiconductors (YC W26); United States; Remote; USD 160.000 - 220.000; Vollzeit

Zusammenfassung

Visibl Semiconductors (YC W26) is seeking an Analog & Mixed-Signal IC Layout Engineer to turn reviewed circuit schematics into robust physical designs for our power-electronics ASIC programs. You’ll own clearly scoped layout blocks and their verification handoffs, collaborating with the analog lead and integration engineers.

You should understand how placement, routing, matching and parasitics affect circuit behavior and be ready to resolve layout tradeoffs with the circuit designer before they

Qualifikationen

• Hands-on ownership of analog or mixed-signal IC layout through tapeout.
• Practical experience with Cadence Virtuoso layout and the DRC, LVS and extraction flows used with a foundry PDK.
• Sound judgment around device matching, parasitic resistance and capacitance, isolation, guard rings, sensitive routing and current-carrying interconnect.
• The ability to read analog schematics, work with circuit designers and turn electrical constraints into a reviewable layout.
• A disciplined approach to verification debug, revision control and clear integration handoffs.
• The ability to work independently on a bounded assignment, communicate progress and raise missing requirements or schedule risks early.

Aufgaben

• Layout planning and implementation. Work from the agreed schematic, PDK and electrical requirements to plan and implement analog and mixed-signal blocks.
• Parasitic-aware design. Collaborate with the analog lead on analog sensing blocks, voltage and current references, comparators, op-amps, bandgap references, DACs, low-noise sensing circuits, high-speed sensing paths, I/O-adjacent blocks, UVLO and support circuits as assigned.
• Physical verification. Run and debug design-rule checking (DRC), layout-versus-schematic (LVS) and parasitic extraction (PEX) using the project’s qualified tools and decks.
• Integration and handoff. Maintain the correct cells, hierarchy, pin interfaces and revision history; coordinate power routing and interfaces with responsible engineers.
• Own the layout and verification deliverables agreed for your assignment; top-level integration work remains with owners.

Kenntnisse

Analog layout ownership

Cadence Virtuoso

DRC LVS PEX

Schematic reading

Verification/debug

Independent worker

Tools

Cadence Virtuoso

Jobbeschreibung

Visibl Semiconductors (YC W26) is seeking an Analog & Mixed-Signal IC Layout Engineer to turn reviewed circuit schematics into robust physical designs for our power-electronics ASIC programs. You’ll own clearly scoped layout blocks and their verification handoffs, collaborating with the analog lead and integration engineers.

You should understand how placement, routing, matching and parasitics affect circuit behavior and be ready to resolve layout tradeoffs with the circuit designer before they