Remote AMS DV Engineer (Analog/Mixed-Signal)

Comunidade Metodista; United States; Remote; USD 90,000 - 150,000; Full time

Job summary

Axiom Software Solutions Limited in the United States is seeking an Analog/Mixed-Signal Design Verification DV Engineer to work remotely. The role focuses on extracting modeling specifications, developing AMS models in SystemVerilog, and building UVM testbenches to verify mixed-signal circuits.

You will run simulations, collaborate with circuit and layout teams to develop timing models, and ensure designs meet functional specs.

Qualifications

• Extract modeling specifications from designers.
• Develop AMS model in System-Verilog.
• Develop UVM Testbench and test cases.
• Run simulations and fix behavioral models with circuit designers.
• Develop timing models with layout engineers.
• Influence design changes to meet specifications.
• Determine root causes of anomalous symptoms in specs/models/testbench/design.
• Support integration of composite models across groups.
• Strong SystemVerilog RTL coding including state machines, adders and multipliers.
• Understand digital design for mixed-signal control loops with Verilog/Verilog-A for analog control.
• Familiarity with behavioral Verilog for analog circuits.
• Write thorough test benches for digital and AMS simulators.
• Deep understanding of constraints for mixed-signal designs, multiple clock domains, and clock gating.
• Familiarity with timing closure and static timing analysis tools.
• Experience with scan chain vector generation and verification.

Responsibilities

• Extract modeling specifications from designers.
• Develop AMS model in System-Verilog.
• Develop UVM Testbench and test cases.
• Run simulation and fix the behavioral model with circuit designer.
• Develop timing model for the circuit with layout engineer.
• Influence design changes to meet functional specifications.
• Determine whether issues arise from specifications, models, testbench, or design.
• Support integration of composite models into larger models maintained by other groups.
• System-Verilog RTL coding including state machines, adders, multipliers, and combinatorial logic.
• Design Verilog/Verilog-A code to control analog circuits (e.g., band-gap, PLL, amplifiers, filters).
• Write behavioral Verilog for analog circuits.
• Write thorough test benches for digital and AMS simulators.
• Understand constraints for mixed-signal designs, multiple clock domains and clock gating.
• Timing closure and static timing analysis tools familiarity.
• Scan chain vector generation and verification.

Skills

SystemVerilog

UVM Testbench

Verilog-A

AMS model development

Digital design for mixed-signal

Clock domain design

Timing closure

Static timing analysis

Testbench development

Circuit verification

RTL coding

Verilog

Analog circuit control

Tools

SystemVerilog tools

Verilog-A tools

Job description

Axiom Software Solutions Limited in the United States is seeking an Analog/Mixed-Signal Design Verification DV Engineer to work remotely. The role focuses on extracting modeling specifications, developing AMS models in SystemVerilog, and building UVM testbenches to verify mixed-signal circuits.

You will run simulations, collaborate with circuit and layout teams to develop timing models, and ensure designs meet functional specs.