R&D Engineer

H.T. Prof Executive Search; Los Angeles (CA); On-site; USD 110,000 - 160,000; Full time

Job summary

A technology solutions provider is seeking a full-time R&D Engineer based in Los Angeles. The role involves designing, simulating, and testing wireless communication systems, with responsibilities including architecture of HDL simulations and automation of testing via scripts. The ideal candidate holds a relevant Bachelor's degree and has significant FPGA design experience, along with proficiency in tools like Xilinx and Vivado. This position follows a hybrid work model, requiring at least three onsite days each week.

Qualifications

• 4 years of experience in FPGA design and testing/verification or 2 years with an MS.
• Proven experience with multiple clock-domain FPGA designs.
• Experience with Tcl or Python scripting.
• Proficiency in Tcl or Python for automation.

Responsibilities

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate testing processes using scripts.
• Collect and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting with logic analyzers.

Skills

FPGA design

HDL testing

Python

Automation scripting

Communication systems

Code coverage

Education

Bachelor of Science in Electrical Engineering or Computer Science

Master of Science in Electrical Engineering

Tools

Xilinx FPGAs

Vivado IDE

MATLAB

Job description

Our client is seeking a full-time R&D Engineer reporting to the Director of R&D Engineering on the R&D Engineering team. The successful individual in this role will participate in the design, simulation, prototyping, and testing of wireless communication and sensing projects and products. This position is on a hybrid schedule, a minimum of 3 days onsite per week is expected. On-site days are: Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate certain testing using scripts.
• Collect, maintain, and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field plus 4 years of demonstrated experience in FPGA design and testing/verification OR 2 years of FPGA experience in design and testing/verification with an MS or advanced degree.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with tcl or python.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• Master of Science degree in Electrical Engineering (MSEE).
• Demonstrated experience with fixed point binary arithmetic, and digital signal processing designs.
• Basic MATLAB skill.
• Experience with communication systems on FPGA or ASIC designs.

COMPENSATION

The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate’s experience and qualifications.