R&D Engineer

Mission Driven Search; Los Angeles, Northern (CA, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

Mission Driven Search is seeking an R&D Engineer to join the team and contribute to design, simulation, prototyping, and testing of wireless communication and sensing projects. The role reports to the R&D Engineering Director and requires hands-on work across HDL, FPGA, and verification tasks.

The position follows a hybrid schedule with a minimum of three onsite days per week (Mondays, Wednesdays, Thursdays).

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or a relevant field with 4 years FPGA design/testing experience or 2 years with an MS or higher.
• Demonstrated experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with TCL or Python.

Responsibilities

• Architect testbenches for full-system HDL simulations.
• Maintain and improve HDL testing infrastructure.
• Automate testing with scripts.
• Collect and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

Skills

FPGA design

HDL testing/verification

Clock-domain design

Xilinx FPGAs

Vivado IDE

Python

Tcl

Education

Bachelor of Science in Electrical Engineering, Computer Science, or relevant field

MS or advanced degree

Tools

Vivado IDE

Xilinx FPGAs/SoCs

Job description

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Our client is seeking a full-time R&D Engineerreporting to the Director of R&D Engineering on the R&D Engineering team. The successful individual in this role will participate in the design, simulation, prototyping, and testing of wireless communication and sensing projects and products. This position is on a hybrid schedule, a minimum of 3 days onsite per week is expected. On-site days are: Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate certain testing using scripts.
• Collect, maintain, and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field plus 4 years of demonstrated experience in FPGA design and testing/verification OR 2 years of FPGA experience in design and testing/verification with an MS or advanced degree.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with tcl or python.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• Master of Science degree in Electrical Engineering (MSEE).
• Demonstrated experience with fixed point binary arithmetic, and digital signal processing designs.
• Basic MATLAB skill.
• Experience with communication systems on FPGA or ASIC designs.

COMPENSATION

The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate’s experience and qualifications.