Mixed Signal Design Verification (MSDV) Engineer

nexperia; Dallas (TX); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

Competitive salary

Health, dental and vision insurance

401(k) with company match

Paid time off and holidays

Professional development and training

Collaborative engineering environment

Opportunities to work on cutting-edge

Job summary

Nexperia is seeking a Mixed Signal Design Verification Engineer in Dallas to lead DV efforts for pre-tapeout verification. You will craft detailed verification plans, develop mixed-signal models, and drive automated regression campaigns across analog and digital teams.

You will coordinate with design, systems, and validation colleagues to ensure complete verification and robust silicon performance, leveraging Cadence tools and UVM-based methodologies.

Qualifications

• Bachelor’s, Master’s or PhD in Electrical Engineering or related field.
• Strong familiarity with analog, digital and mixed-signal design and tool flow.
• Experience with Verilog/Verilog-A/SystemVerilog and UVM for automated regressions.
• Proficiency with Unix shell, TCL, Perl, Python and SKILL scripting.

Responsibilities

• Lead DV activities and drive quality pre-tapeout verification.
• Create pre-Si verification plan and mixed-signal models; run automated regressions to meet coverage goals.
• Interface with systems, applications, test and silicon validation teams to ensure design verification completeness.
• Build cross-functional relationships to identify and solve design problems.
• Analyze simulation results and recommend actionable fixes.
• Participate in design and verification reviews and silicon bring-up.
• Support post-silicon validation and correlate results with simulation.

Skills

Analog/mixed-signal design

DV planning & lead

Automation of regressions

Systems interface

Debugging & problem-solving

Verilog/Verilog-A/SystemVerilog

UVM

Scripting (Python, Perl, TCL, SKILL)

Communication skills

Education

Electrical Engineering or related field

Tools

Cadence Virtuoso

UNIX shell

TCL

Perl

Python

SKILL scripting

Verilog

Verilog-A

SystemVerilog

UVM

Job description

Mixed Signal Design Verification Engineer

Position Summary

Integrated Circuit Solutions (ICS) Group is seeking a highly motivated Mixed Signal Design Verification Engineer with a strong background in analog and mixed-signal IC design verification. In this role, you will be responsible for pre-tapeout verification of silicon design, ensuring the part will meet all stated specifications and behavior and is manufacturable and testable. Familiarity with power converters and the challenges of power design is a plus. This position requires strong communication skills and leadership qualities. The selected individual will assume a technical contributor role with the ability to identify and implement opportunities for continuous improvement and work collaboratively with a diverse team of analog and digital designers, layout engineers, and system architects to ensure first-pass silicon success and high-quality product delivery.

Key Responsibilities

• Operate as DV lead to drive quality product tapeouts
• Develop a detailed pre-Si verification plan, create simulation environments, and mixed-signal behavioral models and work closely with design and systems teams to execute automated regressions to ensure coverage goals are met
• Interface across different functional groups such as systems, applications, test, silicon validation, etc. to ensure product design was verified correctly and completely and that end-product fits customer’s needs
• Build relationships with internal teams by closely interacting with them to identify and solve design related problems
• Analyze simulation results, identify root causes of failures, and provide actionable recommendations.
• Participate in design reviews, verification reviews, and silicon bring-up activities.
• Support post-silicon validation and correlation between simulation and measured silicon performance.

Required Qualifications

• Strong familiarity with EDA design tools such as Cadance Virtuoso design environment
• Strong familiarity with analog, digital and mixed-signal design and tool flow
• Extensive experience with Verilog/Verilog-A/SystemVerilog and Universal Verification Methodology (UVM) to run automated regressions
• Working knowledge of Unix shell, TCL, Perl, Python and SKILL scripting languages
• Excellent analytical, troubleshooting, and communication skills.
• Bachelor’s, Master’s or PhD degrees in Electrical Engineering or related field of study

Preferred Qualifications

• Experience developing verification environment for integrated circuits that incorporate I2C, PMBus or SPI type communication protocols
• Understand power management chip architectures (ideal diodes, e-fuses, switching converters etc)
• Experience with lab validation is a plus
• Understand ESD, reliability, and electro-migration verification
• Experience with semiconductor manufacturing processes and design-for-test methodologies.
• Familiarity with version control systems such as DesignSync, SVN, Git.

Success Factors

The ideal candidate is detail-oriented, analytical, and collaborative, with a passion for delivering robust analog and mixed-signal designs. They thrive in a fast-paced development environment, communicate effectively across cross-functional teams, and are committed to continuous improvement of verification methodologies.

Benefits

• Competitive salary and performance-based incentives
• Comprehensive health, dental, and vision insurance
• Retirement savings plan with company match
• Paid time off and company holidays
• Professional development and training opportunities
• Collaborative and innovative engineering environment
• Opportunities to work on cutting-edge semiconductor technologies

About the team

Join a global team at the forefront of innovation and play a key role in shaping the future of Nexperia’s product offerings.

More information?

For more details please contact: [e-mail]

D&I Statement

As an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.

In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women’s groups. Nexperia is committed to increasing women in management positions to 30% by 2030.

Nexperia is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, color, creed, religion, national origin, ancestry, citizenship status, age, sex or gender (including pregnancy, childbirth and pregnancy‑related conditions), gender identity or expression (including transgender status), sexual orientation, marital status, military service and veteran status, physical or mental disability, genetic information, or any other characteristic protected by applicable federal, state or local laws and ordinances. Nexperia’s management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, TeamNexperian’s activities, access to facilities and programs and general treatment during employment.