CPU Cache Microarchitect/RTL Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

A leading tech company in Beaverton, Oregon, is seeking an experienced micro-architect to develop specifications and own RTL design. Candidates must possess at least a BS and 10+ years in the industry, with expertise in microprocessor architecture and Verilog or VHDL. This role involves collaboration with verification teams and delivering design on multiple performance aspects. The company values diversity and promotes equal opportunity for all applicants.

Qualifications

• 10+ years of relevant industry experience.
• Experience with logic design principles.
• Experience with simulators and waveform debugging.

Responsibilities

• Develop micro-architecture specifications.
• Own RTL design with performance targets.
• Support verification through test bench development.

Skills

Micro-architecture development

RTL design

Verification support

Performance exploration

Design delivery

Microprocessor architecture

Verilog or VHDL

C or C++ programming

Python or Perl scripting

Education

Minimum BS

Job description

Description

• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience with microprocessor architecture
• Experience with logic design principles with timing and power implications
• Experience in Verilog or VHDL
• Experience with simulators and waveform debugging process

Preferred Qualifications

• Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction
• Understanding of low power microarchitecture techniques
• Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
• Experience in C or C++ programming
• Experience using an interpretive language such as Perl or Python

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.