RTL Design Engineer

ALTEN; California (MO); On-site; USD 100,000 - 130,000; Full time

Job summary

A technology consulting firm in California is seeking an experienced RTL Designer to focus on processor datapath components and microarchitecture. The ideal candidate will have over 5 years of RTL design experience, strong Verilog/SystemVerilog skills, and an understanding of CPU datapath design. This role involves collaboration with verification teams and support for front-end design flows, ensuring high-quality implementations.

Qualifications

• 5+ years of RTL design experience.
• Strong skills in Verilog / SystemVerilog.
• Experience with CPU datapath design required.

Responsibilities

• Develop RTL for processor datapath components.
• Design blocks such as ALU, Load/Store units, and more.
• Implement microarchitecture in Verilog/SystemVerilog.

Skills

RTL design experience

Strong Verilog / SystemVerilog

CPU datapath design

Familiarity with vector or matrix compute units

Job description

Responsibilities

• Develop RTL for processor datapath components
• Design blocks such as: ALU, Load/Store units, Vector / Matrix execution units, Register files, Instruction decode / execution pipelines
• Implement microarchitecture in Verilog/SystemVerilog
• Work closely with verification teams to ensure design correctness
• Support front-end design flows (lint, CDC, synthesis)

Requirements

• 5+ years RTL design experience
• Strong Verilog / SystemVerilog
• Experience with CPU datapath design
• Familiarity with vector or matrix compute units

Preferred

• RISC-V architecture knowledge
• Experience in processor pipeline design