Principal Design-for-Test (DFT) Engineer

Celero Communications, Inc.; United States; Remote; USD 140,000 - 190,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal DFT Engineer in Irvine, CA to lead robust Design-for-Test methodologies for high-volume ASIC/SoC production.

You will collaborate with RTL, verification, and physical design teams to implement scan, ATPG, MBIST, and JTAG features, driving sign-off and test readiness through silicon bring-up and failure analysis.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with industry-standard DFT tools (Synopsys, Siemens, Cadence).

Responsibilities

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Skills

Scan insertion

ATPG patterns

MBIST

JTAG

Verilog/SystemVerilog

Python scripting

Linux

Cross-functional

Debugging

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Synopsys TestMAX

TetraMAX

DFT Compiler

Siemens Tessent

Cadence Modus

Job description

Principal Design-for-Test (DFT) Engineer

• Irvine, CA

Principal DFT Engineer

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high-quality, high-volume production of complex ASIC and SoC products.

What You Will Do

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

What You Will Bring

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
• Results-driven engineer with strong debugging abilities.
• Comfortable working in fast-paced cross-functional environments.
• Passion for delivering high-quality silicon products.

Preferred Qualifications

• Experience with advanced-node semiconductor technologies.
• Hands-on experience with MBIST, compression architectures, and JTAG.
• Knowledge of timing closure, physical design impacts, and low-power design techniques.
• Experience supporting silicon validation and manufacturing production ramps.
• Strong communication and cross-functional collaboration skills.

celerocatsone

Javier Leon
Talent Acquisition
619-227-3193 cell/text
[e-mail]
www.celero.inc