Principal Verification Engineer, High-Performance CPU

SiFive, Inc.; Austin (TX); On-site; USD 190,000 - 230,000; Full time

Job summary

SiFive, Inc. in Austin, Texas, is seeking a Principal Design Verification Engineer to lead verification strategy for a high-performance CPU subsystem spanning OoO core development and cache-coherent interconnect behavior.

This principal individual-contributor role requires defining architecture-aware verification strategies, identifying risks early, and elevating verification quality across core and uncore domains.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with depth appropriate for a Principal / T6 role.
• Direct experience with out-of-order core verification and strong understanding of CPU microarchitecture.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics.
• Deep expertise in Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
• Strong software development, scripting, and automation skills for building scalable DV infrastructure and workflows.

Responsibilities

• Lead verification strategy and execution for high-performance CPU subsystem development, with scope spanning OoO core microarchitecture and coherent interconnect/subsystem behavior.
• Own verification planning, execution, debug, coverage analysis, and closure from block level through subsystem integration and signoff.
• Define verification strategies for complex CPU behaviors including branch prediction, instruction fetch, issue/dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
• Define verification strategy and closure criteria for coherent traffic, protocol correctness, ordering rules, backpressure, buffering behavior, arbitration, QoS, and error handling across cache-coherent interconnect paths.
• Drive verification across interface boundaries, bridges, and protocol adaptation paths, including conversion, buffering, and related subsystem-level data movement behavior.
• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models that expose corner cases and improve bug-finding efficiency across both core and uncore verification problems.
• Apply the right verification method for the problem, using simulation, formal techniques, and emulation to improve quality, accelerate turnaround, and strengthen debug efficiency on large subsystem workloads.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve designs from a verification and debugability perspective.
• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Mentor engineers, influence team-wide methodology, and shape reusable verification approaches that benefit future generations of high-performance CPU subsystems.

Skills

CPU verification experience

Out-of-order verification

Cache coherence understanding

Frontend

Midcore

Load-Store Unit

Test planning

Coverage analysis

Debug skills

Scripting

Education

BS/MS/PhD in EE/CE/CS

Job description

SiFive, Inc. in Austin, Texas, is seeking a Principal Design Verification Engineer to lead verification strategy for a high-performance CPU subsystem spanning OoO core development and cache-coherent interconnect behavior.

This principal individual-contributor role requires defining architecture-aware verification strategies, identifying risks early, and elevating verification quality across core and uncore domains.