Principal TPM: Multi-Die ML Accelerator Silicon

Amazon Inc.; Omaha (NE); On-site; USD 204,000 - 275,000; Full time

Job summary

Annapurna Labs, Inc designs the custom silicon powering AWS ML infrastructure, including the Trainium and Inferentia chip families. We seek a Principal Technical Program Manager to own end-to-end program execution for this chip from RTL freeze through tape-out and into production readiness.

This is not a status-reporting role. You will connect a sprawling set of engineering workstreams into a single coherent schedule, identify the real critical path week to week, and drive the cross-functional

Qualifications

• 10+ years of hands-on work managing complex technology projects.
• Deep working knowledge of the chip development lifecycle: RTL verification milestones, physical design convergence, DFT, and timing closure.
• Experience managing programs with external design partners and IP vendors where you don't control the resources but own the outcome.
• Demonstrated ability to build and maintain integrated schedules with real dependency modeling – not just Gantt charts, but an understanding of which paths have float and which don't.

Responsibilities

• Own the integrated schedule and critical path analysis across multiple die tape-outs through engineering samples and production ramp.
• Understand dependency chains deeply enough to calculate the impact of any slip or pull-in, and update the timeline weekly with real data.
• Drive the weekly chip status cadence by synthesizing inputs from RTL/DV, physical design, packaging, power, infrastructure, and post-silicon teams into a single view that tells leadership where we actually stand, including what is getting worse and what needs action.
• Track verification convergence as a leading indicator by monitoring the progression from feature completion through RTL closure, bug trends, and regression pass rates by block.
• Recognize when convergence is stalling and drive the engineering response before downstream milestones are affected.
• Manage the external design partner interface, owning the netlist delivery calendar, tracking your partner's physical design timeline, and negotiating schedule trades with a clear understanding of downstream cost.
• Drive infrastructure readiness and external IP delivery by partnering with compute and EDA platform teams on capacity planning, and tracking third-party PHY, memory interface, and controller IP deliveries against consuming blocks to escape gaps before they become tape-out critical.

Skills

Project management

RTL verification milestones

Physical design convergence

DFT

Timing closure

External partners management

Dependency modeling

Job description

Annapurna Labs, Inc designs the custom silicon powering AWS ML infrastructure, including the Trainium and Inferentia chip families. We seek a Principal Technical Program Manager to own end-to-end program execution for this chip from RTL freeze through tape-out and into production readiness.

This is not a status-reporting role. You will connect a sprawling set of engineering workstreams into a single coherent schedule, identify the real critical path week to week, and drive the cross-functional