Principal Chip Program Manager for Multi‑Die Silicon

Amazon Inc.; Austin (TX); Hybrid; USD 177,000 - 239,000; Full time

Job summary

Annapurna Labs in Austin, TX is seeking a Principal Technical Program Manager to own end-to-end program execution for a next‑gen ML accelerator. You will connect sprawling engineering workstreams into a single schedule, identify critical paths weekly, and drive cross‑functional decisions that keep the program on track.

The role spans RTL, DV, physical design, packaging, and infrastructure, with external partners and IP vendors.

Qualifications

• 10+ years of hands-on program management for complex technology projects.
• Deep knowledge of RTL verification milestones, physical design convergence, DFT, and timing closure.
• Experience managing programs with external design partners and IP vendors.

Responsibilities

• Own the integrated schedule and critical path analysis across multiple die tape-outs through engineering samples and production ramp.
• Drive the weekly chip status cadence by synthesizing inputs from RTL/DV, physical design, packaging, power, infrastructure, and post-silicon teams into a single view for leadership.
• Track verification convergence from feature completion through RTL closure, bug trends, and regression pass rates by block; drive engineering response if convergences stall.
• Manage the external design partner interface, owning the netlist delivery calendar, tracking partner's physical design timeline, and negotiating schedule trades.
• Drive infrastructure readiness and external IP delivery by partnering with compute and EDA platform teams on capacity planning, tracking third-party IP deliveries against consuming blocks.

Skills

Program management

Engineering collaboration

Chip development lifecycle

External partner management

Dependency modeling

Technical communication

Job description

Annapurna Labs in Austin, TX is seeking a Principal Technical Program Manager to own end-to-end program execution for a next‑gen ML accelerator. You will connect sprawling engineering workstreams into a single schedule, identify critical paths weekly, and drive cross‑functional decisions that keep the program on track.

The role spans RTL, DV, physical design, packaging, and infrastructure, with external partners and IP vendors.