Principal TPM, Hardware/Systems — Hybrid & Equity

D-Matrix Corp.

Santa Clara, Northern (CA, KY)

Híbrido

USD 180 000 - 240 000

Tempo integral

14 dias+
Gerador de candidaturas

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Resumo da oferta

d-Matrix is seeking a Principal Technical Program Manager for hardware and systems to drive engineering excellence across the global hardware organization. You will translate company objectives into actionable programs, improve planning, and foster collaboration across regions and domains.

Lead post-silicon to product delivery, align with Product, Hardware, and Manufacturing teams, and manage risks to ensure on-time, high-quality chip and system releases.

Qualificações

  • 10+ years in IC chip/board development or TPM roles.
  • Excellent communication and stakeholder management skills.
  • Experience in complex software/hardware integration.
  • Proven track record leading distributed, multi-region teams.
  • Strong understanding of system development, qualification cycle, and waterfall PM.
  • Experience establishing scalable processes in fast-moving engineering orgs.

Responsabilidades

  • Lead end-to-end program management across post-silicon and hardware development.
  • Coordinate with engineering, product, and manufacturing teams.
  • Define milestones, risk mitigation, and KPIs for project health.
  • Develop playbooks and best practices for cross-functional deliveries.
  • Provide clear leadership updates to executives and partners.

Conhecimentos

Technical PM
Cross-functional
Hardware integration
Stakeholder mgmt
Multi-region
Waterfall mgmt
Process scaling

Ferramentas

JIRA
Smartsheet

Descrição da oferta de emprego

d-Matrix is seeking a Principal Technical Program Manager for hardware and systems to drive engineering excellence across the global hardware organization. You will translate company objectives into actionable programs, improve planning, and foster collaboration across regions and domains.

Lead post-silicon to product delivery, align with Product, Hardware, and Manufacturing teams, and manage risks to ensure on-time, high-quality chip and system releases.

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