Principal SOC Integration Engineer — Memory & System IP

Samsungsemiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

Paid time off 4+ weeks

Fertility/adoption stipend

Onsite cafe and gym

Flexible work policy

Comprehensive benefits package

Job summary

Samsung Semiconductor in San Jose seeks a Principal Engineer, SOC Integration to lead integration of silicon solutions for memory and storage. You will interface with architecture, verification, and physical design teams to enhance memory and storage controllers across modern SoCs.

Focus areas include high-speed interfaces, IP integration (ARM, UCIe, DDR), and coordinating timing, lint, and CDC checks for robust tape-out readiness.

Qualifications

• BS in Computer/Electrical Engineering or Computer Science with 20+ years of experience.
• Hands-on ASIC design flow from design to tape-out.
• Experience with IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA trade-offs.
• Experience in SoC synthesis, timing analysis, lint checks, CDC checks.
• Familiarity with AMBA bus fabric, ARM CPU cores, and ARM Co-sight debug features.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Responsibilities

• Own the integration of SoCs with multiple high-speed interfaces.
• Reviews 3rd party IPs including ARM cores, DDR controller, and UCIe PHY and
• Responsible for integrating the third part IPs with system bus, peripherals and CPU cores.
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

Skills

ASIC design flow

SoC integration

ARM IP integration

UCIe integration

System bus topology

Synthesis & timing analysis

Lint & CDC checks

Education

BS in Computer/Electrical Engineering or Computer Science with 20+ years experience

MS with 18+ years experience

Tools

AMBA bus fabric

ARM CPU cores

UCIe IP

DDR interfaces

Job description

Samsung Semiconductor in San Jose seeks a Principal Engineer, SOC Integration to lead integration of silicon solutions for memory and storage. You will interface with architecture, verification, and physical design teams to enhance memory and storage controllers across modern SoCs.

Focus areas include high-speed interfaces, IP integration (ARM, UCIe, DDR), and coordinating timing, lint, and CDC checks for robust tape-out readiness.