Lead Principal Design Verification Engineer - AI ASICs

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Incentives

Benefits

Job summary

A technology company based in California is seeking a Principal Design Verification Engineer to ensure the quality of next-gen AI connectivity ASICs. This role involves defining verification strategies, owning the verification lifecycle, and mentoring team members. Candidates should have a Bachelor's in Electrical Engineering, over 10 years of relevant experience, and expertise in SystemVerilog. The salary range is between $185,000 to $230,000, depending on experience.

Qualifications

• 10+ years of experience verifying complex SoCs for Server, Storage, and Networking.
• Expert-level proficiency with SystemVerilog/UVM.
• Strong debugging skills working with design teams.

Responsibilities

• Define and execute comprehensive verification strategies.
• Own the full verification lifecycle from planning to coverage closure.
• Partner with teams to develop and execute test plans on emulation platforms.

Skills

SystemVerilog

UVM

Debugging

Hybrid verification methodologies

Test plan development

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering or related field

Tools

Industry-standard simulators

Python

Perl

Job description

A technology company based in California is seeking a Principal Design Verification Engineer to ensure the quality of next-gen AI connectivity ASICs. This role involves defining verification strategies, owning the verification lifecycle, and mentoring team members. Candidates should have a Bachelor's in Electrical Engineering, over 10 years of relevant experience, and expertise in SystemVerilog. The salary range is between $185,000 to $230,000, depending on experience.