Principal Engineer, Digital Verification and Emulation

Ayar Labs; San Jose (CA); On-site; USD 190,000 - 240,000; Full time

Job summary

Ayar Labs in San Jose is seeking a Principal Design Verification Engineer to lead verification strategy for a next-generation silicon photonic chip. You will architect scalable UVM environments, mentor engineers, and drive cross-disciplinary collaboration from concept to tape-out.

You will define verification methodologies, tackle complex system-level challenges, and push for high-quality silicon. This role requires strong SystemVerilog/UVM proficiency and deep experience with ASIC/SoC

Qualifications

• MS in Electrical Engineering, Computer Engineering, or related field.
• Expert-level proficiency in SystemVerilog and UVM.
• Experience building verification environments from scratch (Agents, Scoreboards, Sequencers).
• Deep knowledge of PCIe, AMBA/AXI, UCIe interfaces and related protocols.
• Proficient in scripting for automation (Python, Perl, Tcl, or Shell).
• Ability to drive functional coverage and achieve 100% closure.

Responsibilities

• Architect testbenches: modular, reusable UVM environments for IP blocks and subsystems.
• Set verification methodologies, guidelines, and coverage metrics.
• Collaborate with architects/RTL designers to define verification plans.
• Lead debugging across RTL, firmware, and the verification environment.
• Mentor engineers and conduct code reviews; foster engineering excellence.
• Develop scripts/infrastructure to automate regression testing and coverage.

Skills

SystemVerilog

UVM

Python

RTL verification

Scripting

Education

MS in Electrical/Computer Engineering

Tools

Formal Verification Tools

Emulation Platforms

Job description

Location: San Jose (on-site)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead, architecting scalable verification environments and driving high-quality silicon from concept to tape-out. You will look beyond block-level testing to solve complex system-level challenges, define methodologies, and mentor a growing team of bright engineers.

Essential Functions

• Architect Testbenches: Define and build modular, reusable, and scalable UVM testbench architectures for complex IP blocks and Sub-systems.
• Drive Methodology: Set the standard for verification methodologies, coding guidelines, and coverage metrics. Evaluate and deploy new EDA tools, formal verification techniques, or emulation flows.
• Strategic Planning: Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability.
• Complex Debugging: Lead the effort to debug elusive hardware bugs, root-causing issues across RTL, firmware, and the verification environment.
• Technical Leadership: Mentor senior and junior engineers, conduct code reviews, and foster a culture of engineering excellence.
• Automation & Efficiency: Develop scripts and infrastructure to automate regression testing, performance analysis, and coverage closure.

Basic Qualifications

• Experience: MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification.
• Core Competency: Expert-level proficiency in SystemVerilog and UVM.
• Architecture: Proven track record of building verification environments from scratch (Agents, Scoreboards, Sequencers, etc.).
• Protocols: Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe).
• Scripting: Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell).
• Coverage: Experience defining functional coverage groups and driving logic verification to 100% closure.

Preferred Qualifications

• Formal Verification: Experience with formal property checking (VC Formal) and writing SVA (SystemVerilog Assertions).
• Emulation & Acceleration: Hands-on experience with hardware emulation platforms.
• Processor Knowledge: Familiarity with RISC-V or ARM architecture and coherency protocols.
• Mixed Signal: Experience in Analog/Mixed-Signal (AMS) verification.
• Modeling: Experience with C/C++ or SystemC modeling for reference models.
• Experience working on digital designs with multiple clock domains and clock dividers.
• Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment.
• Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends.
• Experience with verification of HBM memory interfaces (PHY and controller).
• Experience in formal model equivalence checking tools and verification methodology.
• Programming experience in Python.

Salary range: $190,000 - $240,000

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.