Senior Wireline SerDes Design Engineer

Langham Recruitment; San Jose (CA); Vor Ort; USD 150.000 - 300.000; Vollzeit

Benefits dieser Stelle

Comprehensive healthcare

401(k)

Paid leave

Additional benefits

Zusammenfassung

Langham Recruitment is seeking an experienced Analog/Mixed-Signal Design Engineer for a growing semiconductor company in San Jose, CA. You will develop high-speed SerDes and optical transceiver technologies from architecture to silicon validation and production.

Requirements include an MS or PhD in Electrical Engineering or Physics, strong high-speed analog CMOS design experience, and proficiency with Cadence tools and mixed-signal simulations.

Qualifikationen

• MS or PhD in Electrical Engineering, Physics or a related field.
• Strong high-speed analog CMOS circuit design experience.
• Understanding of deep-submicron processes and wireline transceiver design.
• Experience with SerDes, Cadence design tools and mixed-signal simulation.

Aufgaben

• Evaluate architectures for advanced high-speed SerDes and wireline transceivers.
• Design and verify analog/mixed-signal CMOS circuits, including drivers, samplers, ADCs/DACs, PLLs and clocking circuits.
• Collaborate with DSP and systems teams to optimise performance.
• Evaluate and debug silicon, supporting products through to high-volume production.

Kenntnisse

Analog CMOS design

SerDes

Mixed-signal simulation

Cadence tools

Ausbildung

MS or PhD in Electrical Engineering or Physics

Tools

Cadence

Jobbeschreibung

A growing semiconductor company is developing next-generation connectivity solutions for AI datacentres, cloud infrastructure and high-performance computing.

They're looking for an experienced Analog/Mixed-Signal Design Engineer to develop high-speed wireline SerDes and optical transceiver technologies, from circuit architecture through to silicon validation and production.

The Role

• Evaluate architectures for advanced high-speed SerDes and wireline transceivers.


• Design and verify analog/mixed-signal CMOS circuits, including drivers, samplers, ADCs/DACs, PLLs and clocking circuits.


• Collaborate with DSP and systems teams to optimise performance.


• Evaluate and debug silicon, supporting products through to high-volume production.

What We're Looking For

• MS or PhD in Electrical Engineering, Physics or a related field.


• Strong high-speed analog CMOS circuit design experience.


• Understanding of deep-submicron processes and wireline transceiver design.


• Experience with SerDes, Cadence design tools and mixed-signal simulation.


• $150,000-$300,000 base salary, depending on experience.


• Performance bonus.


• Comprehensive healthcare, 401(k), paid leave and additional benefits.