Principal Physical Design Engineer - High-Impact ASIC/SoC Role

Delos Data Inc; Palo Alto (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Delos Data Inc, a California startup, seeks a Principal Physical Design Engineer to shape challenging physical implementation and drive performance, power, area, and schedule targets. You will own complex blocks from floorplan through signoff and lead a hands-on PD team in a fast-paced environment.

This early member role requires deep expertise in floorplanning, routing, timing closure, power integrity, and integration with RTL/architecture teams.

Qualifications

• 10+ years of ASIC or SoC physical design experience with multiple tapeouts.
• Expert-level floorplanning, placement, CTS, routing, timing closure, ECOs, and physical verification.
• Strong timing closure across multi-mode and multi-corner scenarios.
• Deep knowledge of power delivery, IR drop, electromigration, and signal integrity.
• Experience with Cadence and/or Synopsys physical implementation and signoff tools.

Responsibilities

• Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
• Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power and routability.
• Drive placement, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.
• Lead timing convergence across block boundaries and support top-level timing convergence.
• Provide technical leadership and mentorship to other PD engineers.

Skills

ASIC/SoC PD

Floorplanning

Timing closure

Power/IR drop

Clock design

EDA tools (Cadence/Synopsys)

Scripting (Tcl/Python/Perl)

Cross-functional leadership

Debug complex problems

Tools

Cadence

Synopsys

Job description

Delos Data Inc, a California startup, seeks a Principal Physical Design Engineer to shape challenging physical implementation and drive performance, power, area, and schedule targets. You will own complex blocks from floorplan through signoff and lead a hands-on PD team in a fast-paced environment.

This early member role requires deep expertise in floorplanning, routing, timing closure, power integrity, and integration with RTL/architecture teams.