Principal Hardware Architect

Piper Companies; San Jose (CA); On-site; USD 210,000 - 260,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

401(k)

PTO

Job summary

Piper Companies is seeking a Principal Hardware Architect in the San Jose, CA area to lead architecture and design of high-speed, high-power networking boards and support ASIC bring-up. This onsite role calls for a senior electrical engineering leader who can guide complex hardware platforms through the entire lifecycle.

The ideal candidate will have 10+ years in electrical engineering with deep expertise in high-speed PCB design, SI/PI and thermal management, and hands-on board bring-up in

Qualifications

• 10+ years of electrical engineering experience with deep expertise in high-speed, high-power PCB design.
• End-to-end ownership of board development lifecycle including manufacturing support and bring-up.
• Strong background in signal integrity, power integrity, and thermal considerations for dense, high-performance systems.
• Hands-on testing and validation with cross-functional teams including ASIC and mechanical engineering.

Responsibilities

• Lead the architecture and design of complex test and validation boards supporting custom ASIC bring-up and evaluation.
• Own the full board development lifecycle, from schematic capture through layout oversight, manufacturing, and initial bring-up.
• Provide technical leadership on signal integrity, power integrity, and thermal design for extremely high-speed, high-power systems.
• Collaborate closely with ASIC design teams to understand silicon internals, define test strategies, and validate functionality.
• Partner with mechanical engineering and test teams during board bring-up, debug, and system-level validation.

Skills

Electrical engineering

PCB design

Signal integrity

Power integrity

Thermal design

Board bring-up

ASIC collaboration

Job description

Piper Companies is seeking a Principal Hardware Architect around San Jose, CA to join a cutting‑edge organization developing advanced networking hardware purpose‑built for AI data centers. Principal Hardware Architect will need to sit onsite 5 days a week near the San Jose CA area. The Hardware Systems Architect role is ideal for a senior electrical engineering leader with deep expertise in high‑speed, high‑power board design who can guide complex hardware platforms used to bring up and validate next‑generation custom ASICs.

Responsibilities of the Principal Hardware Architect:

• Lead the architecture and design of complex test and validation boards supporting custom ASIC bring‑up and evaluation.
• Own the full board development lifecycle, from schematic capture through layout oversight, manufacturing, and initial bring‑up.
• Provide technical leadership on signal integrity, power integrity, and thermal design for extremely high‑speed, high‑power systems.
• Collaborate closely with ASIC design teams to understand silicon internals, define test strategies, and validate functionality.
• Partner with mechanical engineering and test teams during board bring‑up, debug, and system‑level validation.

Qualifications of the Principal Hardware Architect:

• 10+ years of electrical engineering experience with deep expertise in high‑speed, high‑power PCB design.
• Proven experience owning end‑to‑end board development, including manufacturing support and hands‑on bring‑up.
• Strong background in signal integrity (SI), power integrity (PI), and thermal considerations for dense, high‑performance systems.
• Hands‑on experience with board testing and validation in collaboration with mechanical and cross‑functional engineering teams.
• Background in telecom or networking hardware, ideally Ethernet switching or ASIC‑adjacent systems.

Compensation for the Principal Hardware Architect:

• Salary range: $210,000-$260,000
• Comprehensive benefits package including medical, dental, vision, 401(k), and PTO

This job opens for applications on 07/20/2026. Applications for this job will be accepted for at least 30 days from the posting date.