Sr Principal Engineer, Application Engineering & System Design

Fox Point Recruitment LLC; Santa Clara (CA); On-site; USD 200,000 - 266,400; Full time

Benefits offered by this job

Relocation assistance

Visa sponsorship available

Onsite 5 days/week

Job summary

Fox Point Recruitment LLC is seeking a Senior Principal Engineer for Board & System Hardware Design in Santa Clara, onsite, full-time. You will guide customer hardware design-in for Ethernet Switch and UALink platforms, coordinating with silicon, hardware, and field teams.

You will shape 112G–224G PAM4 SerDes designs, drive DFx, lead bring-up, and act as a key technical bridge to ensure designs are robust for high-volume production.

Qualifications

• 15+ years of hardware design experience for high-speed networking or compute systems.
• 7+ years SerDes board/system design (25G NRZ to 112G/224G PAM4).
• Full lifecycle ownership of complex high-speed boards from architecture to bring-up.
• Experience delivering reference designs enabling adoption.
• Strong PCB stack-up and material selection expertise.
• Power architecture for high-current ASICs and PDN design.
• Thermal design and mechanical integration for high-power systems.
• SI/PI knowledge and ability to review simulations.

Responsibilities

• Provide system architecture and hardware design guidance for board and system hardware.
• Lead hardware bring-up support and root-cause debugging during labs and early production.
• Drive DFx initiatives for smooth production transitions with ODM/CM partners.
• Lead design-in reviews of schematics, PCB stack-ups, and architectures.
• Develop and support reference designs for new silicon with internal teams.

Skills

15+ years hardware design experience

SerDes design 25G-112G/224G PAM4

High-speed PCB stack-up design

Power delivery (PDN) design

Thermal design for high-power systems

SI/PI knowledge

Customer-facing engagements

Technical training delivery

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

PhD in Electrical Engineering

Related field

Tools

Cadence Allegro/Sigrity

Mentor Xpedition/HyperLynx

Job description

Job Title:Senior Principal Engineer, Hardware Application Engineering — Board & System Design

Location: Santa Clara, CA (Onsite — 5 days/week)

Department: Engineering / Architecture

Group: Customer Solutions Group

Position Type: Full-Time (New Position)

Base Compensation: USD $200,000 – $266,400 / year (No variable compensation/bonus flexibility)

Relocation Assistance: Available

Visa Sponsorship: Available

About the Team & Role

Our Customer Solutions Group is the frontline technical partner to the world’s most demanding infrastructure customers—megascale data centers, cloud providers, and AI system builders. We turn cutting-edge silicon into deployable platforms by working shoulder-to-shoulder with customer engineering teams from early architecture through production ramp.

As Senior Principal Engineer for Board & System Hardware Design, you will serve as the senior technical authority guiding customer hardware design-in on proprietary Ethernet Switch and UALink platforms. You will act as the crucial technical bridge between internal silicon teams, hardware engineering, and field operations.

This is a deep individual contributor role with a strong system-design and productization focus. Your primary mission is to ensure that customers’ next-generation switches, AI fabric platforms, and networking systems are designed right the first time—performant, manufacturable, reliable, and ready for high-volume production.

Technical Leadership & Customer Enablement

System Architecture & Hardware Design Guidance

• Drive PCB stack-up strategy and material selection (low-loss laminates, copper roughness, glass weave, via construction) to meet high-speed performance and cost targets.
• Guide customers on power delivery architecture, including PDN design, multi-rail sequencing, decoupling strategy, and tolerance analysis for high-current ASICs.
• Advise on thermal design, mechanical integration, and cooling strategies (air, liquid, immersion) to meet performance and reliability targets in real deployments.
• Provide guidance on signal and power integrity (SI/PI), reviewing customer simulations and contributing simulations directly when required.
• Drive Design for Reliability, Manufacturability, and Testability (DFx)—ensuring smooth transitions to production at ODM/CM partners.

Next-Gen Tech & Cross-Functional Influence

• Provide technical leadership on 112G and 224G PAM4 SerDes designs today, and help shape the hardware approach for next-generation 448G systems and open AI fabric standards.
• Lead hardware bring-up support, root‑cause debug, and issue resolution during customer lab phases and early production.
• Act as a vital field‑feedback channel to internal silicon and hardware teams—influencing silicon I/O, package, power, and reference design choices based on real‑world customer deployment learnings.

Candidate Profile & Qualifications

Must-Have Requirements

• Education: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Overall Experience: 15+ years in hardware design, development, and validation of high‑speed networking or compute systems.
• SerDes Expertise: 7+ years of dedicated experience in board and system design for high‑speed platforms involving modern SerDes (25G NRZ through 112G/224G PAM4).
• Board Lifecycle: Proven full‑lifecycle ownership of complex high‑speed boards (architecture, schematic, layout guidance, bring‑up).
• Reference Designs: Demonstrated experience defining and delivering reference designs that enabled customer or internal platform adoption.

• Technical Depth:
  • Strong expertise in high‑layer‑count PCB stack‑up design and material selection.
  • Deep experience with power architecture for high‑current ASICs (PDN design, sequencing, decoupling, tolerance analysis).
  • Solid background in thermal design and mechanical integration for high‑power network/AI systems.
  • Working knowledge of SI/PI principles (ability to review and run targeted simulations).
  • Hands‑on lab experience with hardware bring‑up, debugging, and root‑cause analysis using industry‑standard equipment.
  • Deep understanding of high‑speed interfaces: Ethernet, PCIe, DDR, advanced SerDes, and modern power delivery.
• Soft Skills & Leadership:
  • Proven customer‑facing experience supporting complex technical engagements.
  • Ability to develop and deliver technical training to engineering audiences.
  • Exceptional communication skills with a track record of influencing senior customer engineering teams across geographies.

Preferred Qualifications

• Direct experience with Ethernet switch platforms (any tier) and/or emerging open AI fabric standards.
• Experience designing or reviewing hardware platforms targeting megascale data center deployments.
• Background in reference platform design and customer enablement for silicon-based solutions.
• Familiarity with ODM/CM manufacturing flows, including DFM/DFT, qualification, and reliability testing.
• Experience with advanced cooling approaches (liquid, immersion) for high‑power AI/networking platforms.
• Fluency with EDA tools in either Cadence (Allegro/Sigrity) or Mentor/Siemens (Xpedition/HyperLynx) ecosystems (tool‑agnostic experts are welcome).
• Track record of influencing silicon and platform roadmaps based on field insights.

Leadership, Impact & Work Environment

• Leadership & Mentorship: Set the technical bar for board and system design quality across the most strategic customer engagements; mentor engineers and raise collective team expertise.
• Travel: Project‑driven travel to customer sites, ODMs, and labs as needed (not continuous).

• Serve as the primary senior technical advisor to customer hardware teams designing platforms around company Ethernet switches and UALink silicon from early architecture through production ramp.
• Lead design‑in reviews of customer schematics, PCB stack‑ups, and overall system architectures, identifying risks early and guiding customers to best‑in‑class implementations.
• Define, develop, and support reference designs for new silicon—partnering with silicon, packaging, and internal hardware engineering teams from early product definition through customer release.
• Own architecture, schematic, layout guidance, and bring‑up of company reference and evaluation platforms, applying full lifecycle hands‑on expertise.
• Develop and deliver high‑impact technical training to customers and internal teams covering proprietary silicon, reference designs, high‑speed design best practices, and productization methodologies.