Principal FPGA/RTL Design Engineer - Signal Processing Lead

motorolasolutions; Los Angeles (CA); Hybrid; USD 195,000 - 235,000; Full time

Benefits offered by this job

Incentive Bonus Plans

Medical, Dental, Vision benefits

401K with Company Match

Paid Holidays

Generous Paid Time Off

Job summary

Silvus Technologies is seeking a Principal FPGA/RTL Design Engineer in West Los Angeles, CA, to report to the Director of FPGA Engineering. The role spans concept to field deployment, focusing on efficient signal processing algorithms for Silvus’ MIMO wireless systems.

This hybrid position requires at least three onsite days weekly (Mon, Wed, Thu). Candidates typically have 10+ years RTL/FPGA experience, Xilinx FPGAs, and Vivado expertise; U.S. Person status is required for federal contracts.

Qualifications

• BS in Electrical Engineering, Computer Science, or related field.
• Minimum 10 years RTL design and FPGA implementation; or 8 years with MS; or 6 years with PhD.
• Experience with fixed-point arithmetic and DSP designs.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• U.S. Person due to federal contract; background check and drug test.

Responsibilities

• Digital design architecting for wireless projects.
• Fixed-point design of signal processing blocks with systems engineers.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; use of logic analyzers.
• Support to RF and Software Engineering teams.

Skills

RTL design

FPGA implementation

Digital signal processing

Clock domain crossing

Verilog/VHDL coding

Education

Bachelor of Science in Electrical Engineering, Computer Science, or related field

Tools

Vivado IDE

Xilinx FPGAs/SoCs

MATLAB

Python

Perl

Job description

Silvus Technologies is seeking a Principal FPGA/RTL Design Engineer in West Los Angeles, CA, to report to the Director of FPGA Engineering. The role spans concept to field deployment, focusing on efficient signal processing algorithms for Silvus’ MIMO wireless systems.

This hybrid position requires at least three onsite days weekly (Mon, Wed, Thu). Candidates typically have 10+ years RTL/FPGA experience, Xilinx FPGAs, and Vivado expertise; U.S. Person status is required for federal contracts.