Principal FPGA Design Engineer

Cadence; San Jose (CA); On-site; USD 131,000 - 245,000; Full time

Job summary

A leading company in electronic design is seeking a Principal FPGA Design Engineer in San Jose. You will be integral to developing, validating, and documenting FPGA digital designs, requiring strong expertise in FPGA IP development and design verification. Join a collaborative and innovative environment, leveraging state-of-the-art technology while focusing on your professional growth and well-being.

Benefits

Paid vacation and holidays

401(k) plan with employer match

Employee stock purchase plan

Variety of medical, dental, and vision options

Qualifications

• Master's degree in Electrical Engineering and 5+ years of experience required.
• Experience with FPGA design and verification using Verilog essential.
• Detailed knowledge of industry-standard interfaces like PCI Express and I2C.

Responsibilities

• Developing FPGA IPs for Protium platform including design, verification, and documentation.
• Enhancing current IPs and developing new ones.
• Debug and fix internal regression failures for FPGA IPs.

Skills

FPGA design

Verification

Debugging

Linux

Scripting

Education

Master's degree in Electrical Engineering

Tools

Verilog

Vivado

Cadence Simulators Incisive

Job description

Join to apply for the Principal FPGA Design Engineer role at Cadence

Join to apply for the Principal FPGA Design Engineer role at Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
  
  

Job Responsibility

Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs.

• Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users;
• Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;
• Enhancing current IPs as well as developing new IPs.
• Debug and fix internal regression failures for FPGA IPs.
• Documentation of IPs
  
  

Position Requirements/Qualifications

• Master degree in Electrical Engineering with 5+ years of experience
• Experience with FPGA design and verification using Verilog
• Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route
• Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software
• Experience using Linux servers, Script development using Shell/Perl/TCL
• Experience using Cadence Simulators Incisive or Xcelium
• Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI
  
  

The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Software Development

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