Principal FPGA Design Engineer - FPGA IPs (R48198/rj)

Cadence; San Jose (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

An innovative company is seeking a talented FPGA Engineer to join their dynamic team. In this role, you will design and verify cutting-edge FPGA intellectual properties for the Protium platform, contributing to the rapid development of prototypes and pre-silicon validation. With a focus on enhancing existing IPs and creating new ones, your expertise will be essential in debugging and ensuring the quality of hardware. This position offers the opportunity to work with advanced technologies in a collaborative environment, where your contributions will significantly impact the world of technology. If you have a passion for engineering and a desire to innovate, this is the perfect opportunity for you.

Benefits

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Paid paternity leave

Tuition assistance

Qualifications

• 5+ years of experience in FPGA design and verification.
• Master's degree in Electrical Engineering required.

Responsibilities

• Developing FPGA IPs for Protium platform including design and verification.
• Debugging and fixing internal regression failures for FPGA IPs.

Skills

FPGA Design

Verification using Verilog

Debugging FPGAs

Timing Closure

Documentation

Education

Master's degree in Electrical Engineering

Tools

Vivado

Cadence Simulators (Incisive, Xcelium)

Job description

EDA Recruiter Connecting EEs and CEs to EDA Careers at Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. With Cadence Protium prototyping platforms, design and verification teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and hardware regressions.

Protium is a leading product in the FPGA Emulation/Prototyping domain. This role is to design, verify, close timing, and validate hardware of the FPGA IPs.

• Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation, and releasing the IPs to end users;
• Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;
• Enhancing current IPs as well as developing new IPs;
• Debugging and fixing internal regression failures for FPGA IPs;
• Documentation of IPs.

The ideal candidate will have the following skills and experience:

• Master's degree in Electrical Engineering with 5+ years of experience;
• Experience with FPGA design and verification using Verilog;
• Experience with high-end Xilinx (AMD) FPGAs including using Vivado tool for simulation, place and route;
• Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software;
• Experience using Cadence Simulators Incisive or Xcelium;
• Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering and Information Technology

Industries

Computer Hardware Manufacturing

Benefits:

• Medical insurance
• Vision insurance
• 401(k)
• Paid maternity leave
• Paid paternity leave
• Tuition assistance